參數(shù)資料
型號： TMS418169P-70
廠商： Texas Instruments, Inc.
英文描述： 1048576-WORD BY 16-BIT EXTENDED DATA OUT HIGH-SPEED DRAMS
中文描述： 1048576字由16位擴(kuò)充數(shù)據(jù)輸出高速DRAM等
文件頁數(shù)： 14/67頁
文件大?。?/td> 1464K
代理商： TMS418169P-70
TMS55160, TMS55161, TMS55170, TMS55171
262144 BY 16-BIT MULTIPORT VIDEO RAMS
SMVS464
–
MARCH1996
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
byte operation
Byte operation can be applied in DRAM read cycles, write cycles, block-write cycles, load-write-mask-register
cycles and load-color-register cycles. In byte operation, the column address (A0
–
A8) is latched at the first falling
edge of CASx. In read cycles, CASL enables the lower byte (DQ0
–
DQ7) and CASU enables the upper byte
(DQ8
–
DQ15) (see Figure 4).
Row
th(CLCA)
RAS
tsu(CA)
Column
Lower Byte Output
Upper Byte
Output
ta(C)
CASL
CASU
A0
–
A8
DQ0
–
DQ7
DQ8
–
DQ15
TRG
ta(G)
ta(C)
See
“
switching characteristics over recommended ranges of supply voltage and operating free-air temperature
”
table.
See
“
timing requirements over recommended ranges of supply voltage and operating free-air temperature
”
table.
Figure 4. Example of a Byte-Read Cycle
相關(guān)PDF資料
PDF描述
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TMS4256-10FME 制造商:TI 制造商全稱:Texas Instruments 功能描述:262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES
TMS4256-10FML 制造商:TI 制造商全稱:Texas Instruments 功能描述:262,144-BIT DYNAMIC RANDOM-ACCESS MEMORIES
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