參數(shù)資料
型號： TMS320C6727B_07
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： Floating-Point Digital Signal Processors
中文描述： 浮點數(shù)字信號處理器
文件頁數(shù)： 99/116頁
文件大?。?/td> 999K
代理商： TMS320C6727B_07
www.ti.com
4.16.2 RTI/Digital Watchdog Registers Description(s)
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
The digital watchdog is disabled by default. Once enabled, a sequence of two 16-bit key values (0xE51A
followed by 0xA35C in two separate writes) must be continually written to the key register before the
watchdog counter counts down to zero; otherwise, the DSP will be reset. This feature can be used to
provide an added measure of robustness against a software failure. If the application fails and ceases to
write to the watchdog key; the watchdog will respond by resetting the DSP and thereby restarting the
application.
Note that Counter 0 and Compare 0 are used by DSP BIOS to generate the tick counter it requires;
however, Capture 0 is still available for use by the application as well as the remaining RTI resources.
Table 4-38
is a list of the RTI registers.
Table 4-38. RTI Registers
BYTE ADDRESS
REGISTER NAME
DESCRIPTION
Device-Level Configuration Registers Controlling RTI
Selects the sources for the RTI input captures from among the six McASP DMA event.
0x4000 0014
CFGRTI
RTI Internal Registers
Global Control Register. Starts / stops the counters.
Reserved bit.
Capture Control. Controls the capture source for the counters.
Compare Control. Controls the source for the compare registers.
Free-Running Counter 0. Current value of free-running counter 0.
Up-Counter 0. Current value of prescale counter 0.
Compare Up-Counter 0. Compare value compared with prescale counter 0.
Capture Free-Running Counter 0. Current value of free-running counter 0 on external
event.
Capture Up-Counter 0. Current value of prescale counter 0 on external event.
Free-Running Counter 1. Current value of free-running counter 1.
Up-Counter 1. Current value of prescale counter 1.
Compare Up-Counter 1. Compare value compared with prescale counter 1.
Capture Free-Running Counter 1. Current value of free-running counter 1 on external
event.
Capture Up-Counter 1. Current value of prescale counter 1 on external event.
Compare 0. Compare value to be compared with the counters.
Update Compare 0. Value to be added to the compare register 0 value on compare
match.
Compare 1. Compare value to be compared with the counters.
Update Compare 1. Value to be added to the compare register 1 value on compare
match.
Compare 2. Compare value to be compared with the counters.
Update Compare 2. Value to be added to the compare register 2 value on compare
match.
Compare 3. Compare value to be compared with the counters.
Update Compare 3. Value to be added to the compare register 3 value on compare
match.
Reserved bit.
Reserved bit.
Set Interrupt Enable. Sets interrupt enable bits int RTIINTCTRL without having to do a
read-modify-write operation.
Clear Interrupt Enable. Clears interrupt enable bits int RTIINTCTRL without having to
do a read-modify-write operation.
Interrupt Flags. Interrupt pending bits.
0x4200 0000
0x4200 0004
0x4200 0008
0x4200 000C
0x4200 0010
0x4200 0014
0x4200 0018
0x4200 0020
RTIGCTRL
Reserved
RTICAPCTRL
RTICOMPCTRL
RTIFRC0
RTIUC0
RTICPUC0
RTICAFRC0
0x4200 0024
0x4200 0030
0x4200 0034
0x4200 0038
0x4200 0040
RTICAUC0
RTIFRC1
RTIUC1
RTICPUC1
RTICAFRC1
0x4200 0044
0x4200 0050
0x4200 0054
RTICAUC1
RTICOMP0
RTIUDCP0
0x4200 0058
0x4200 005C
RTICOMP1
RTIUDCP1
0x4200 0060
0x4200 0064
RTICOMP2
RTIUDCP2
0x4200 0068
0x4200 006C
RTICOMP3
RTIUDCP3
0x4200 0070
0x4200 0074
0x4200 0080
Reserved
Reserved
RTISETINT
0x4200 0084
RTICLEARINT
0x4200 0088
RTIINTFLAG
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