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參數(shù)資料
| 型號(hào)： | TMS320C6727B_07 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Floating-Point Digital Signal Processors |
| 中文描述： | 浮點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 37/116頁(yè) |
| 文件大?。?/td> | 999K |
| 代理商： | TMS320C6727B_07 |
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www.ti.com
4.7 Power Supplies
4.7.1
Power-Supply Sequencing
4.7.2
Power-Supply Decoupling
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
For more information regarding TI’s power management products and suggested devices to power TI
DSPs, visit
www.ti.com/dsppower
.
This device does not require specific power-up sequencing between the DV
DD
and CV
DD
voltage rails;
however, there are some considerations that the system designer should take into account:
1. Neither supply should be powered up for an extended period of time (>1 second) while the other
supply is powered down.
2. The I/O buffers powered from the DV
DD
rail also require the CV
DD
rail to be powered up in order to be
controlled; therefore, an I/O pin that is supposed to be 3-stated by default may actually drive
momentarily until the CV
DD
rail has powered up. Systems should be evaluated to determine if there is
a possibility for contention that needs to be addressed. In most systems where both the DV
DD
and
CV
DD
supplies ramp together, as long as CV
DD
tracks DV
DD
closely, any contention is also mitigated by
the fact that the CV
DD
rail would reach its specified operating range well before the DV
DD
rail has fully
ramped.
In order to properly decouple the supply planes from system noise, place as many capacitors (caps) as
possible close to the DSP. The core supply caps can be placed in the interior space of the package and
the I/O supply caps can be placed around the exterior space of the package. For the BGA package, it is
recommended that both the core and I/O supply caps be placed on the underside of the PCB. For the
TQFP package, it is recommended that the core supply caps be placed on the underside of the PCB and
the I/O supply caps be placed on the top side of the PCB.
Both core and I/O decoupling can be accomplished by alternating small (0.1
μ
F) low ESR ceramic bypass
caps with medium (0.220
μ
F) low ESR ceramic bypass caps close to the DSP power pins and adding
large tantalum or ceramic caps (ranging from 10
μ
F to 100
μ
F) further away. Assuming 0603 caps, it is
recommended that at least 6 small, 6 medium, and 4 large caps be used for the core supply and 12 small,
12 medium, and 4 large caps be used for the I/O supply.
Any cap selection needs to be evaluated from an electromagnetic radiation (EMI) point-of-view; EMI varies
from one system design to another so it is expected that engineers alter the decoupling capacitors to
minimize radiation. Refer to the
High-Speed DSP Systems Design Reference Guide
(literature number
SPRU889) for more detailed design information on decoupling techniques.
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Peripheral and Electrical Specifications
37
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