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參數(shù)資料
| 型號(hào)： | TMS320C6727B_07 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Floating-Point Digital Signal Processors |
| 中文描述： | 浮點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 44/116頁 |
| 文件大?。?/td> | 999K |
| 代理商： | TMS320C6727B_07 |
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4.10 External Interrupts
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
The C672x DSP has no dedicated general-purpose interrupt pins, but the dMAX can be used in
combination with a McASP AMUTEIN signal to provide external interrupt capability. There is a multiplexer
for each McASP, controlled by the CFGMCASP0/1/2 registers, which allows the AMUTEIN input for that
McASP to be sourced from one of seven I/O pins on the DSP. Once a pin is configured as an AMUTEIN
source, a very short pulse (two SYSCLK2 cycles or more) on that pin will generate an event to the dMAX.
This event can trigger the dMAX to generate a CPU interrupt by programming the assoicated Event Entry.
There are a few additional points to consider when using the AMUTEIN signal to enable external interrupts
as described above. The I/O pin selected by the CFGMCASP0/1/2 registers must be configured as a
general-purpose input pin within the associated peripheral. Also, the AMUTEIN signal should be disabled
within the corresponding McASP so that AMUTE is not driven when AMUTEIN is active. This can be done
by clearing the INEN bit of the AMUTE register inside the McASP. Finally, AMUTEIN events are logically
ORed with the McASP transmit and receive error events within the dMAX; therefore, the ISR that
processes the dMAX interrupt generated by these events must discern the source of the event.
The EMIF EM_WAIT pin has the ability to generate an NMI (INT1) based upon a rising edge on the
EM_WAIT pin. Note that while this interrupt is connected to the CPU NMI (non-maskable interrupt), it is
actually maskable through the EMIF control registers. In fact, the default state for this interrupt is disabled.
Also, interrupt generation always occurs on a rising edge of EM_WAIT; the polarity selection for wait state
generation has no effect on the interrupt polarity. The EM_WAIT pin should remain asserted for at least
two SYSCLK3 cycles to ensure that the edge is detected.
Peripheral and Electrical Specifications
44
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