參數資料
型號： TMS320C6727B_07
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： Floating-Point Digital Signal Processors
中文描述： 浮點數字信號處理器
文件頁數： 85/116頁
文件大?。?/td> 999K
代理商： TMS320C6727B_07
www.ti.com
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
Table 4-28. General Timing Requirements for SPIx Slave Modes
(1)
NO.
MIN
MAX
UNIT
greater of 8P or
9
t
c(SPC)S
Cycle Time, SPIx_CLK, All Slave Modes
256P
ns
100 ns
greater of 4P or
10
t
w(SPCH)S
Pulse Width High, SPIx_CLK, All Slave Modes
ns
45 ns
greater of 4P or
11
t
w(SPCL)S
Pulse Width Low, SPIx_CLK, All Slave Modes
ns
45 ns
Polarity = 0, Phase = 0,
to SPIx_CLK rising
Polarity = 0, Phase = 1,
to SPIx_CLK rising
Polarity = 1, Phase = 0,
to SPIx_CLK falling
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK rising
Polarity = 0, Phase = 1,
from SPIx_CLK falling
Polarity = 1, Phase = 0,
from SPIx_CLK falling
Polarity = 1, Phase = 1,
from SPIx_CLK rising
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
Polarity = 0, Phase = 0,
to SPIx_CLK falling
Polarity = 0, Phase = 1,
to SPIx_CLK rising
Polarity = 1, Phase = 0,
to SPIx_CLK rising
Polarity = 1, Phase = 1,
to SPIx_CLK falling
Polarity = 0, Phase = 0,
from SPIx_CLK falling
Polarity = 0, Phase = 1,
from SPIx_CLK rising
Polarity = 1, Phase = 0,
from SPIx_CLK rising
Polarity = 1, Phase = 1,
from SPIx_CLK falling
2P
Setup time, transmit data
written to SPI and output
onto SPIx_SOMI pin before
initial clock edge from
master.
2P
12
t
su(SOMI_SPC)S
ns
2P
2P
2P + 15
2P + 15
Delay, subsequent bits
valid on SPIx_SOMI after
transmit edge of SPIx_CLK
13
t
d(SPC_SOMI)S
ns
2P + 15
2P + 15
0.5t
c(SPC)S
– 10
Output hold time,
SPIx_SOMI valid after
receive edge of SPIxCLK,
except for final bit
(4)
0.5t
c(SPC)S
– 10
14
t
oh(SPC_SOMI)S
ns
0.5t
c(SPC)S
– 10
0.5t
c(SPC)S
– 10
0.5P + 15
0.5P + 15
Input Setup Time,
SPIx_SIMO valid before
receive edge of SPIx_CLK
15
t
su(SIMO_SPC)S
ns
0.5P + 15
0.5P + 15
0.5P + 5
0.5P + 5
Input Hold Time,
SPIx_SIMO valid after
receive edge of SPIx_CLK
16
t
ih(SPC_SIMO)S
ns
0.5P + 5
0.5P + 5
(1)
(2)
P = SYSCLK2 period
First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on
SPIx_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPIx_SIMO.
Measured from the termination of the write of new data to the SPI module, as evidenced by new output data appearing on the
SPIx_SOMI pin. In analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to
the SPI module by either the DSP CPU or the dMAX.
The final data bit will be held on the SPIx_SOMI pin until the SPIDAT0 or SPIDAT1 register is written with new data.
(3)
(4)
Submit Documentation Feedback
Peripheral and Electrical Specifications
85
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