參數(shù)資料
型號: TMS320C6727B_07
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: Floating-Point Digital Signal Processors
中文描述: 浮點(diǎn)數(shù)字信號處理器
文件頁數(shù): 51/116頁
文件大?。?/td> 999K
代理商: TMS320C6727B_07
www.ti.com
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
SPRS370C–SEPTEMBER 2006–REVISED OCTOBER 2007
Table 4-9. EMIF Asynchronous Interface Timing Requirements
(1)(2)
NO.
MIN
MAX UNIT
Input setup time, read data valid on EM_D[31:0] before EM_CLK
rising
Input hold time, read data valid on EM_D[31:0] after EM_CLK rising
Setup time, EM_WAIT valid before EM_CLK rising edge
Hold time, EM_WAIT valid after EM_CLK rising edge
Pulse width of EM_WAIT assertion and deassertion
Delay from EM_WAIT sampled deasserted on EM_CLK rising to
beginning of HOLD phase
Setup before end of STROBE phase (if no extended wait states are
inserted) by which EM_WAIT must be sampled asserted on
EM_CLK rising in order to add extended wait states.
28
t
su(EM_DV-EM_CLKH)A
5
ns
29
30
31
33
t
h(EM_CLKH-EM_DIV)A
t
su(EM_CLKH-EM_WAITV)A
t
h(EM_CLKH-EM_WAITIV)A
t
w(EM_WAIT)A
2
5
0
ns
ns
ns
ns
2E + 5
34
t
d(EM_WAITD-HOLD)A
4E
(3)
ns
35
t
su(EM_WAITA-HOLD)A
4E
(3)
ns
(1)
(2)
(3)
E = SYSCLK3 (EM_CLK) period.
These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes.
These parameters specify the number of EM_CLK cycles of latency between EM_WAIT being sampled at the device pin and the EMIF
entering the HOLD phase. However, the asynchronous setup (parameter 30) and hold time (parameter 31) around each EM_CLK edge
must also be met in order to ensure the EM_WAIT signal is correctly sampled.
In
Figure 4-13
, it appears that there are more than 4 EM_CLK cycles encompassed by parameter 35. However, EM_CLK cycles that are
part of the extended wait period should not be counted; the 4 EM_CLK requirement is to the start of where the HOLD phase would
begin if there were no extended wait cycles.
(4)
Table 4-10. EMIF Asynchronous Interface Switching Characteristics
(1)
NO.
PARAMETER
MIN
10
7.5
MAX UNIT
100-MHz EMIF Frequency
133-MHz EMIF Frequency
1
t
c(EM_CLK)
Cycle time, EMIF clock EM_CLK
ns
2
17
18
21
22
23
24
25
26
27
32
t
w(EM_CLK)
t
dis(EM_CLKH-EM_DHZ)S
t
ena(EM_CLKH-EM_DLZ)S
t
d(EM_CLKH-EM_CS2V)A
t
d(EM_CLKH-EM_WE_DQMV)A
t
d(EM_CLKH-EM_AV)A
t
d(EM_CLKH-EM_DV)A
t
d(EM_CLKH-EM_OEV)A
t
d(EM_CLKH-EM_RW)A
t
dis(EM_CLKH-EM_DDIS)A
t
d(EM_CLKH-EM_WE)A
Pulse width, high or low, EMIF clock EM_CLK
Delay time, EM_CLK rising to EM_D[31:0] 3-stated
Output hold time, EM_CLK rising to EM_D[31:0] driving
Delay time, from EM_CLK rising edge to EM_CS[2] valid
Delay time, EM_CLK rising to EM_WE_DQM[3:0] valid
Delay time, EM_CLK rising to EM_A[12:0] and EM_BA[1:0] valid
Delay time, EM_CLK rising to EM_D[31:0] valid
Delay time, EM_CLK rising to EM_OE valid
Delay time, EM_CLK rising to EM_RW valid
Delay time, EM_CLK rising to EM_D[31:0] 3-stated
Delay time, EM_CLK rising to EM_WE valid
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7.7
1.15
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
(1)
These parameters apply to memories selected by EM_CS[2] in both normal and NAND modes.
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