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參數(shù)資料
| 型號： | TMP470R1B768PGE |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16/32-Bit RISC Flash Microcontroller |
| 中文描述： | 16/32位RISC閃存微控制器 |
| 文件頁數(shù)： | 30/50頁 |
| 文件大小： | 393K |
| 代理商： | TMP470R1B768PGE |
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Switching Characteristics over Recommended Operating Conditions for External Clocks
(1)(2)(3)
(see
Figure 6
and
Figure 7
)
TMS470R1B768
16/32-Bit RISC Flash Microcontroller
SPNS108A–AUGUST 2005–REVISED AUGUST 2006
PARAMETER
TEST CONDITIONS
SYSCLK or MCLK
(4)
ICLK: X is even or 1
(5)
ICLK: X is odd and not 1
(5)
SYSCLK or MCLK
(4)
ICLK: X is even or 1
(5)
ICLK: X is odd and not 1
(5)
N is even and X is even or odd
N is odd and X is even
N is odd and X is odd and not 1
N is even and X is even or odd
N is odd and X is even
N is odd and X is odd and not 1
MIN
MAX
UNIT
0.5t
c(SYS)
– t
f
0.5t
c(ICLK)
– t
f
0.5t
c(ICLK)
+ 0.5t
c(SYS)
– t
f
0.5t
c(SYS)
– t
r
0.5t
c(ICLK)
– t
r
0.5t
c(ICLK)
– 0.5t
c(SYS)
– t
r
0.5t
c(ECLK)
– t
f
0.5t
c(ECLK)
– t
f
0.5t
c(ECLK)
+ 0.5t
c(SYS)
– t
f
0.5t
c(ECLK)
– t
r
0.5t
c(ECLK)
– t
r
0.5t
c(ECLK)
– 0.5t
c(SYS)
– t
r
t
w(COL)
Pulse duration, CLKOUT low
ns
t
w(COH)
Pulse duration, CLKOUT high
ns
t
w(EOL)
Pulse duration, ECLK low
ns
t
w(EOH)
Pulse duration, ECLK high
ns
(1)
(2)
(3)
(4)
(5)
X = {1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16}. X is the interface clock divider ratio determined by the PCR0[4:1] bits in the SYS module.
N = {1 to 256}. N is the ECP prescale value defined by the ECPCTRL[7:0] register bits in the ECP module.
CLKOUT/ECLK pulse durations (low/high) are a function of the OSCIN pulse durations when PLLDIS is active.
Clock source bits are selected as either SYSCLK (CLKCNTL[6:5] = 11 binary) or MCLK (CLKCNTL[6:5] = 10 binary).
Clock source bits are selected as ICLK (CLKCNTL[6:5] = 01 binary).
Figure 6. CLKOUT Timing Diagram
Figure 7. ECLK Timing Diagram
30
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