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參數(shù)資料
| 型號： | TMP470R1B768PGE |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 16/32-Bit RISC Flash Microcontroller |
| 中文描述： | 16/32位RISC閃存微控制器 |
| 文件頁數(shù)： | 10/50頁 |
| 文件大?。?/td> | 393K |
| 代理商： | TMP470R1B768PGE |
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www.ti.com
TMS470R1B768
16/32-Bit RISC Flash Microcontroller
SPNS108A–AUGUST 2005–REVISED AUGUST 2006
Table 2. Terminal Functions (continued)
TERMINAL
INTERNAL
PULLUP/
PULLDOWN
(3)
SERIAL PERIPHERAL INTERFACE 5 (SPI5)
SPI5 clock. SPI5CLK can be programmed as a GIO pin.
SPI5 chip enable. SPI5ENA can be programmed as a GIO pin.
IPD (20 μA)
SPI5 slave chip select. SPI5SCS can be programmed as a GIO pin.
SPI5 data stream. Slave in/master out. Can be programmed as a GIO pin.
SPI5 data stream. Slave out/master in. Can be programmed as a GIO pin.
ZERO-PIN PHASE-LOCKED LOOP (ZPLL)
Crystal connection pin or external clock input
External crystal connection pin
Enable/disable the ZPLL. The ZPLL can be bypassed and the oscillator
IPD (20 μA)
becomes the system clock. If not in bypass mode, TI recommends that this
pin be connected to ground or pulled down to ground by an external resistor.
SERIAL COMMUNICATIONS INTERFACE 1 (SCI1)
IPD (20 μA)
SCI1 clock. SCI1CLK can be programmed as a GIO pin.
IPU (20 μA)
SCI1 data receive. SCI1RX can be programmed as a GIO pin.
IPU (20 μA)
SCI1 data transmit. SCI1TX can be programmed as a GIO pin.
SERIAL COMMUNICATIONS INTERFACE 2 (SCI2)
IPD (20 μA)
SCI2 clock. SCI2CLK can be programmed as a GIO pin.
IPU (20 μA)
SCI2 data receive. SCI2RX can be programmed as a GIO pin.
IPU (20 μA)
SCI2 data transmit. SCI2TX can be programmed as a GIO pin.
SYSTEM MODULE (SYS)
Bidirectional pin. CLKOUT can be programmed as a GIO pin or the output of
IPD (20 μA)
SYSCLK, ICLK, or MCLK.
Input master chip power-up reset. External V
CC
monitor circuitry must assert
IPD (20 μA)
a power-on reset.
Bidirectional reset. The internal circuitry can assert a reset, and an external
system reset can assert a device reset.
IPU (20 μA)
On this pin, the output buffer is implemented as an open drain (drives low
only). To ensure an external reset is not arbitrarily generated, TI recommends
that an external pullup resistor be connected to this pin.
WATCHDOG/REAL-TIME INTERRUPT (WD/RTI)
Analog watchdog reset. The AWD pin provides a system reset if the WD KEY
is not written in time by the system, providing an external RC network circuit
is connected. If the user is not using AWD, TI recommends that this pin be
connected to ground or pulled down to ground by an external resistor.
IPD (20 μA)
For more details on the external RC network circuit, see the
TMS470R1x
System Module Reference Guide
(literature number SPNU189) and the
application note
Analog Watchdog Resistor, Capacitor and Discharge Interval
Selection Constraints
(literature number SPNA005).
TEST/DEBUG (T/D)
IPD (20 μA)
Test clock. TCK controls the test hardware (JTAG).
Test data in. TDI inputs serial data to the test instruction register, test data
IPU (20 μA)
register, and programmable test address (JTAG).
Test data out. TDO outputs serial data from the test instruction register, test
IPD (20 μA)
data register, identification register, and programmable test address (JTAG).
TYPE
(1)(2)
DESCRIPTION
NAME
NO.
SPI5CLK
SPI5ENA
SPI5SCS
SPI5SIMO
SPI5SOMI
60
61
46
58
59
3.3-V I/O
OSCIN
OSCOUT
13
12
1.8-V I
1.8-V O
PLLDIS
73
3.3-V I
SCI1CLK
SCI1RX
SCI1TX
89
91
90
3.3-V I/O
3.3-V I/O
3.3-V I/O
SCI2CLK
SCI2RX
SCI2TX
45
43
44
3.3-V I/O
3.3-V I/O
3.3-V I/O
CLKOUT
83
3.3-V I/O
PORRST
32
3.3-V I
RST
15
3.3-V I/O
AWD
72
3.3-V I/O
TCK
76
3.3-V I
TDI
74
3.3-V I
TDO
75
3.3-V O
10
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