參數(shù)資料
型號： TMP470R1B768PGE
廠商： Texas Instruments, Inc.
英文描述： 16/32-Bit RISC Flash Microcontroller
中文描述： 16/32位RISC閃存微控制器
文件頁數(shù)： 17/50頁
文件大小： 393K
代理商： TMP470R1B768PGE
www.ti.com
Interrupt Priority (IEM to CIM)
TMS470R1B768
16/32-Bit RISC Flash Microcontroller
SPNS108A–AUGUST 2005–REVISED AUGUST 2006
Interrupt requests originating from the B768 peripheral modules (i.e., SPI1, SPI2, or SPI3; SCI1 or SCI2; HECC1
or HECC2; RTI; etc.) are assigned to channels within the 48-channel interrupt expansion module (IEM) where,
via programmable register mapping, these channels are then mapped to the 32-channel central interrupt
manager (CIM) portion of the SYS module.
Programming multiple interrupt sources in the IEM to the same CIM channel effectively shares the CIM channel
between sources.
The CIM request channels are maskable so that individual channels can be selectively disabled. All interrupt
requests can be programmed in the CIM to be of either type:
Fast interrupt request (FIQ)
Normal interrupt request (IRQ)
The CIM prioritizes interrupts. The precedence of request channels decrease with ascending channel order in
the CIM (0 [highest] and 31 [lowest] priority). For IEM-to-CIM default mapping, channel priorities, and their
associated modules, see
Table 7
.
Table 7. Interrupt Priority (IEM and CIM)
DEFAULT CIM INTERRUPT
LEVEL/CHANNEL
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
MODULES
INTERRUPT SOURCES
IEM CHANNEL
SPI1
RTI
RTI
RTI
SPI2
GIO
SPI1 end-transfer/overrun
COMP2 interrupt
COMP1 interrupt
TAP interrupt
SPI2 end-transfer/overrun
GIO interrupt A
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
RESERVED
HET
SPI4
SCI1/SCI2
SCI1
RESERVED
SPI5
HECC1
RESERVED
SPI3
MibADC
SCI2
DMA
HECC3
SCI1
System
RESERVED
HET
HECC1
RESERVED
SCI2
MibADC
DMA
GIO
MibADC
HECC3
HET interrupt 1
SPI4 end-transfer/overrun
SCI1 or SCI2 error interrupt
SCI1 receive interrupt
SPI5 end-transfer/overrun
HECC1 interrupt A
SPI3 end-transfer/overrun
MibADC end event conversion
SCI2 receive interrupt
DMA interrupt 0
HECC3 interrupt A
SCI1 transmit interrupt
SW interrupt (SSI)
HET interrupt 2
HECC1 interrupt B
SCI2 transmit interrupt
MibADC end Group 1 conversion
DMA interrupt 1
GIO interrupt B
MibADC end Group 2 conversion
HECC3 interrupt B
17
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