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參數(shù)資料
| 型號： | TMP320C40 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 53/62頁 |
| 文件大?。?/td> | 1066K |
| 代理商： | TMP320C40 |
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SGUS017H
–
OCTOBER 1993
–
REVISED OCTOBER 2001
53
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
timing parameters for communication-token transfer sequence, output to an input port [P = t
c(H)
]
(see Figure 26)
NO.
’
320C40-40*
’
320C40-50*
’
320C40-60*
UNIT
MIN
MAX
MIN
MAX
1
td(CRQL-CAL)T
Delay time, CREQx low to start of CACKx going low for
token-request acknowledge
P+5
2P+26
P+5
2P+22
ns
2
td(CRDYL-CAL)T
Delay time, start of CRDYx low at end of word transfer out to
start of CACKx going low
P+6
2P+27
P+6
2P+27
ns
3
td(CAL-CD)I
Delay time, start of CACKx going low to CxD7
–
CxD0 change
from outputs to inputs
0.5P
–
8
0.5P+8
0.5P
–
8
0.5P+8
ns
4
td(CAL-CRDY)T
Delay time, start of CACKx going low to CRDYx change from
an input to output, high level
0.5P
–
8
0.5P+8
0.5P
–
8
0.5P+8
ns
5
td(CRQH-CRQ)T
Delay time, CREQx high to CREQx change from an input to
output, high level
4
22
4
22
ns
6
td(CRQH-CA)T
Delay time, start of CREQx high to CACKx change from
output to an input
4
22
4
22
ns
7
td(CRQH-CS)T
Delay time, start of CREQx high to CSTRBx change from
output to an input
4
22
4
22
ns
8
td(CRQH-CRQL)T
Delay time, CREQx high to CREQx low for the next token
request
These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal
pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the
maximum delay occurs when the input condition occurs just after H1 falling.
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
P
–
4
2P+8
P
–
4
2P+8
ns
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