參數(shù)資料
型號： TMP320C40
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 46/62頁
文件大?。?/td> 1066K
代理商： TMP320C40
SGUS017H
–
OCTOBER 1993
–
REVISED OCTOBER 2001
46
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
timing parameters of IIOFx changing from input to output mode (see Figure 19)
NO.
320C40-40
320C40-50
320C40-60
UNIT
MIN
MAX
MIN
MAX
1
td(H1L-IFIO)
Delay time, H1 low to IIOFx switching from input to output
16
14
ns
Execution of
Load of IIOF
1
H3
H1
TYPE Bit
IIOFx pins
Figure 19. Change of IIOFx From Input to Output Mode
timing parameters for RESET (see Figure 20)
NO.
320C40-40
MIN
11
320C40-50
MIN
11
320C40-60
MIN
11
UNIT
MAX
tc(CI)
MAX
tc(Cl)*
MAX
tc(Cl)*
1
tsu(RESET-CIL)
td(CIH-H1H)
td(CIH-H1L)
Setup time, RESET before CLKIN low
ns
2.1
Delay time, CLKIN high to H1 high
2
12
2
10
2
10
ns
2.2
Delay time, CLKIN high to H1 low
2
12
2
10
2
10
ns
3
tsu(RESETH-H1L)
Setup time, RESET high before H1 low and
after ten H1 clock cycles
13
13
13
ns
4.1
td(CIH-H3L)
td(CIH-H3H)
Delay time, CLKIN high to H3 low
2
12
2
10
2
10
ns
4.2
Delay time, CLKIN high to H3 high
2
12
2
10
2
11
ns
5
tdis(H1H-DZ)
Disable time, H1 high to (L)Dx in
high-impedance state
13*
13*
13*
ns
6
tdis(H3H-AZ)
Disable time, H3 high to (L)Ax in
high-impedance state
9*
9*
9*
ns
7
td(H3H-CONTROLH)
Delay time, H3 high to control signals high
[low for (L)PAGEx]
9*
9*
9*
ns
8
td(H1H-IACKH)
Delay time, H1 high to IACK high
9*
9*
9*
ns
9
tdis(RESETL-ASYNCHZ)
Disable time, RESET low to asynchronous
reset signals in the high-impedance state
21*
21*
21*
ns
10
td(RESETH-COMMH)
Delay time, RESET high to asynchronous reset
signals high
15*
15*
15*
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
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