參數(shù)資料
型號(hào)： TMP320C40
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 52/62頁(yè)
文件大小： 1066K
代理商： TMP320C40
SGUS017H
–
OCTOBER 1993
–
REVISED OCTOBER 2001
52
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
timing parameters for communication-token transfer sequence, input to an output port [P = t
c(H)
]
(see Figure 25)
NO.
’
320C40-40
*
’
320C40-50
*
’
320C40-60*
UNIT
MIN
MAX
1
td(CAL-CS)T
Delay time, CACKx low to CSTRBx change from input to a high-level output
0.5P+ 6
1.5P+ 22
ns
2
td(CAL-CRQH)T
Delay time, CACKx low to start of CREQx going high for token-request
acknowledge
P + 5
2P + 26
ns
3
td(CRQH-CRQ)T
Delay time, start of CREQx going high to CREQx change from output to an input
0.5P
–
5
0.5P+ 13
ns
4
td(CRQH-CA)T
Delay time, start of CREQx going high to CACKx change from an input to an
output level high
0.5P
–
5
0.5P+13
ns
4.1
td(CRQH-CD)T
Delay time, start of CREQx going high to CxD7
–
CxD0 change from inputs driven
to outputs driven
0.5P
–
5
0.5P+13
ns
4.2
td(CRQH-CRDY)T
Delay time, start of CREQx going high to CRDYx change from an output to an
input
0.5P
–
5
0.5P+13
ns
5
td(CRQH-CSL)T
Delay time, start of CREQx going high to CSTRBx low for start of word transfer
out
1.5P
–
8
1.5P+ 9
ns
6
td(CRDYL-CSL)T
These timing parameters result from synchronizer delays and are referenced from the falling edge of H1. The inputs (that cause the output-signal
pins to change values) are sampled on H1 falling. The minimum delay occurs when the input condition occurs just before H1 falling, and the
maximum delay occurs when the input condition occurs just after H1 falling.
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
Delay time, CRDYx low at end of word input to CSTRBx low for word output
3.5P+12
5.5P+ 48
ns
CREQx
CACKx
CSTRBx
CxD7
–
CxD0
CRDYx
= when signal is an input (clear = when signal is an output)
6
3
4
1
4.1
4.2
Valid Data Out
2
5
NOTE A: Before the token exchange, CREQx and CRDYx are output signals asserted by the SMJ320C40 that is receiving data. CACKx,
CSTRBx, and CxD7
–
CxD0 are input signals asserted by the device sending data to the
’
C40; these are asynchronous with respect to
the H1 clock of the receiving SMJ320C40. After token exchange, CACKx, CSTRBx, and CxD7
–
CxD0 become output signals, and
CREQx and CRDYx become inputs.
Figure 25. Communication-Token Transfer Sequence, Input to an Output Port [P=t
c(H)
]
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