參數(shù)資料
型號： TMP320C40
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 37/62頁
文件大?。?/td> 1066K
代理商： TMP320C40
SGUS017H
–
OCTOBER 1993
–
REVISED OCTOBER 2001
37
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
timing parameters for a memory read/write [(L)STRBx = 0] (see Note 6, Figure 10, and Figure 11)
NO.
320C40-40
MIN
320C40-50
MIN
320C40-60
MIN
UNIT
MAX
MAX
MAX
1
td(H1L-SL)
td(H1L-SH)
td(H1H-RWL)
td(H1L-A)
tsu(D-H1L)R
th(H1L-D)R
tsu[(L)RDY-H1L]
th[H1L-(L)RDY]
td(H1L-ST)
td(H1H-RWH)W
tv(H1L-D)W
th(H1H-D)W
Delay time, H1 low to (L)STRBx low
0*
10
0*
10
0*
8
ns
2
Delay time, H1 low to (L)STRBx high
0*
10
0*
10
0*
8
ns
3
Delay time, H1 high to (L)R/Wx low
0*
9
0*
9
0*
8
ns
4
Delay time, H1 low to (L)Ax valid
0*
10
0*
9
0*
8
ns
5
Setup time, (L)Dx valid before H1 low (read)
15
10
9
ns
6
Hold time, (L)Dx after H1 low (read)
0
0
0
ns
7
Setup time, (L)RDYx valid before H1 low
25
20
18*
ns
8
Hold time, (L)RDYx after H1 low
0
0
0
ns
8.1
Delay time, H1 low to (L)STAT3
–
(L)STAT0 valid
10
10
8
ns
9
Delay time, H1 high to (L)R/Wx high (write)
9
9
0*
8
ns
10
Valid time, (L)Dx after H1 low (write)
16
16
13
ns
11
Hold time, (L)Dx after H1 high (write)
0
0
0
ns
12
td(H1H-A)
Delay time, H1 high to address valid on back-to-back
write cycles
13
13
8
ns
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 6: For consecutive reads, (L)R/Wx stays high and (L)STRBx stays low.
6
H3
H1
(L)R/Wx
(L)Ax
(L)Dx
(L)RDYx
(L)STRBx
(L)STAT3
–
(L)STAT0
5
3
1
2
4
8
7
8.1
Figure 10. Memory-Read-Cycle Timing [(L)STRBx = 0]
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