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參數(shù)資料
| 型號： | TMP320C40 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 47/62頁 |
| 文件大?。?/td> | 1066K |
| 代理商： | TMP320C40 |
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1
1
S
–
–
P
–
1
4
PARAMETER MEASUREMENT INFORMATION
(L)PAGE0
–
(L)PAGE1
(see Note C)
Control Signals
(see Note C)
(L)Dx
(see Note A)
RESET
(see Notes E and F)
1
2.1
4.1
6
7
8
3
2.2
4.2
C
7
X2/CLKIN
H1
H3
(L)Ax
(see Note B)
IACK
Asynchronous Reset
Signals (see Note D)
Asynchronous Reset
Signals (see Note E)
Ten H1 Clock Cycles
5
9
9
10
Hi-Z
Hi-Z
Hi-Z
Hi-Z
NOTES: A. In this figure, (L)Dx includes D31
–
D0, LD31
–
D0, and CxD7
–
CxD0.
B. (L)Ax includes A30
–
A0 and LA30
–
LA0.
C. Control signals LSTRB0, LSTRB1, STRB0, STRB1, (L)STAT3
–
(L)STAT0, (L)LOCK, (L)R/W0, and (L)R/W1 go high while (L)PAGE0 and (L)PAGE1 go low.
D. Asynchronous reset signals that go into high impedance after RESET goes low include TCLK0, TCLK1, IIOF3
–
IIOF0, and the communication-port control signals
CREQx, CACKy, CSTRBy, and CRDYx (where x = 0, 1, or 2, and y = 3, 4, or 5).
(At reset, ports 0, 1, and 2 become outputs, and ports 3, 4, and 5 become inputs.)
E. Asynchronous reset signals that go to a high-logic level after RESET goes low include CREQy, CACKx, CSTRBx, and CRDYy (where x = 0, 1, or 2, and y = 3,
4, or 5).
F. RESET is an asynchronous input and can be asserted at any point during a clock cycle. If the specified timings are met, the exact sequence shown will occur;
otherwise, an additional delay of one clock cycle can occur.
Figure 20. RESET Timing
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