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參數(shù)資料
| 型號： | TMP320C40 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 51/62頁 |
| 文件大小： | 1066K |
| 代理商： | TMP320C40 |
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SGUS017H
–
OCTOBER 1993
–
REVISED OCTOBER 2001
51
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
communication-port byte timing parameters (write and read) (see Note 12 and Figure 24)
NO.
’
320C40-40
’
320C40-50
’
320C40-60
UNIT
MIN
MAX
1
tsu(CD-CSL)W
td(CRDYL-CSH)W
th(CRDYL-CD)W
td(CRDYH-CSL)W
tc(BYTE)
td(CSL-CRDYL)R
tsu(CSH-CD)R
th(CRDYL-CD)R
td(CSH-CRDYH)R
tc(BYTE) max = (
means the value under max for parameter 6 in the table
—
a value of 10 ns). This assumes that two
’
C40s are connected.
* On products compliant to MIL-PRF-38535, this parameter is not production tested.
NOTE 12: Communication port timing does not include line length delay.
Setup time, CxDx data valid before CSTRBx low (write)
2
ns
2
Delay time, CRDYx low to CSTRBx high (write)
0*
12
ns
3
Hold time, CxDx after CRDYx low (write)
1
ns
4
Delay time, CRDYx high to CSTRBx low for subsequent bytes (write)
0*
12
ns
5
Cycle time, byte transfer
44
ns
6
Delay time, CSTRBx low to CRDYx low (read)
0*
10
ns
7
Setup time, CxDx valid after CSTRBx high (read)
0
ns
8
Hold time, CxDx valid after CRDYx low (read)
2
ns
9
Delay time, CSTRBx high to CRDYx high (read)
0*
10
ns
+
+
+
) where boxed numbers refer to the max values for corresponding parameters in the above table (for example,
CREQx
CACKx
CSTRBx
CxDx
CRDYx
(a) WRITE TIMING
(b) READ TIMING
1
4
7
6
8
2
3
5
9
5
= when signal is an input (clear = when signal is an output)
Valid Data
Valid
Figure 24. Communication-Port Byte Timing (Write and Read)
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