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參數(shù)資料
| 型號： | TMC2301 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 15, 18, 20 MHz Image Resampling Sequencer(15, 18, 20 MHz圖像再采樣序列發(fā)生器) |
| 中文描述： | 15，18，20 MHz的圖像重采樣音序器（15，18，20 MHz的圖像再采樣序列發(fā)生器） |
| 文件頁數(shù)： | 9/26頁 |
| 文件大?。?/td> | 237K |
| 代理商： | TMC2301 |
PRODUCT SPECIFICATION
TMC2301
9
Test
Mode
(TM)
This mode is available for user inspection
of the coefficient data. The source image
and coefficient addresses are calculated
by an internal 28-bit accumulator. When
TM is 1 (HIGH), the sign bit, normally
discarded, and the lower 11 bits of
internal data are substituted for the upper
12 bits appearing at the source address
port (X) during a standard transform
cycle. This allows user verification of
algorithm mathematics during debug.
Since the TM bit is registered and cannot
be changed during a single clock cycle,
two distinct clock cycles are required to
access both the MSW and LSW of the
internal accumulator. See Figure 3.
Figure 3. Test Mode Data Routing
X
11-0
/T
11-0
CA
7-4
CA
3-0
TEST
MODE
T
11
65-2301-07
INTERNAL
ACCUMULATOR
WALK COUNTER
12
11
1
4
4
8
4
SIGN
12
4
11
Table 1. Parameter Registers – Row Sequencer
Addr
0000
0001
0010
Name
XMIN
XMAX
X
0
(LSW)
Description
Left side of Source Window
Right side of Source Window
Source starting point –
X coordinate
Source starting point –
X coordinate
Mode Select Bits
Row/Row first differential
Row/Row first differential
Test Mode, Field of View
Row/Column first differential
Row/Column first differential
Resampling/Filtering Kernel
Mixed second differential
0011
X
0
(MSW)
0011
0100
0101
0101
0110
0111
0111
1000
Controls
dX/dU
0
(LSW)
dX/dU
0
(MSW)
TM, FOV
dX/dV
0
(LSW)
dX/dV
0
(MSW)
Kernel
d
2
X/dUdV
(LSW)
d
2
X/dUdV
(MSW)
d
2
X/dU
2
(LSW)
d
2
X/dU
2
(MSW)
d
2
X/dV
2
(LSW)
1001
Mixed second differential
1010
1011
1100
Row second differential
Row second differential
Row/Column second
differential
Row/Column second
differential
Left edge of Final Image
Right edge of Final Image
1101
d
2
X/dV
2
(MSW)
1110
1111
UMIN
UMAX
Table 2. Parameter Registers – Column
Sequencer
Addr
0000
0001
0010
Name
YMIN
YMAX
Y
0
(LSW)
Description
Top of Source Window
Bottom of Source Window
Source starting point –
Y coordinate
Source starting point –
Y coordinate
Mode Select Bits
Column/Row first differential
Column/Row first differential
Test Mode, field of View
Column/Column first
differential
Column/Column first
differential
Resampling/Filtering Kernel
Sure
Mixed second differential
Mixed second differential
Column/Row second
differential
Column/Row second
differential
Column second differential
Column second differential
Top edge of Final Image
Bottom edge of Final Image
0011
Y
0
(MSW)
0011
0100
0101
0101
0110
Controls
dY/dU
0
(LSW)
dY/dU
0
(MSW)
TM, FOV
dY/dV
0
(LSW)
0111
dY/dV
0
(MSW)
0111
Kernel
1000
1001
1010
d
2
Y/dUdV (LSW)
d
2
Y/dUdV (MSW)
d
2
Y/dU
2
(LSW)
1011
d
2
Y/dU
2
(MSW)
1100
1101
1110
1111
d
2
Y/dV2 (LSW)
d
2
Y/dV
2
(MSW)
VMIN
VMAX
相關PDF資料 |
PDF描述 |
|---|---|
| TMC2302A | Image Manipulation Sequencer |
| TMC2302AH5C | Image Manipulation Sequencer |
| TMC2302AH5C1 | Image Manipulation Sequencer |
| TMC2302AKEC | Image Manipulation Sequencer |
| TMC2302AKEC1 | Image Manipulation Sequencer |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302A | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AH5C | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AH5C1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AKEC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
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