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參數(shù)資料
| 型號： | TMC2301 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 15, 18, 20 MHz Image Resampling Sequencer(15, 18, 20 MHz圖像再采樣序列發(fā)生器) |
| 中文描述： | 15，18，20 MHz的圖像重采樣音序器（15，18，20 MHz的圖像再采樣序列發(fā)生器） |
| 文件頁數(shù)： | 6/26頁 |
| 文件大?。?/td> | 237K |
| 代理商： | TMC2301 |
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TMC2301
PRODUCT SPECIFICATION
6
LDR
A5
38
Load Parameter Data Registers.
The data held in all
transformation parameter preload registers are latched into the
working registers when the registered input LDR is HIGH. When
LDR is LOW, the working parameters remain unchanged. See
Figure 4.
No Operation.
The Clock is overidden when the registered input
NOOP is LOW, holding each address generator in their current
state. Also, the output buffers for the address busses X
11-0
and
CA
7-0
are forced to the high impedance state. This allows the
user access to all external memory. When NOOP goes HIGH,
normal operation resumes on the next clock cycle.
Target Memory Output Enable.
The target memory outputs
UWRI and address bus U
11-0
are in the high-impedance state
when the registered Output Enable input is HIGH. When OETA is
LOW, they are enabled on the next clock cycle.
Target Memory Write Enable.
After the end of each interpolation
"walk," the Target Memory (U or V) Write Enable goes LOW for
one clock cycle. See Figure 9. This registered output is forced to
the high impedance state when OETA is HIGH.
Parameter Write Enable.
The registered Write Enable input
allows the transformation parameters to be written into the
preload register indicated by the address at the B input port when
LOW. See Figure 4.
NOOP
B5
37
OETA
B1
45
UWRI
K3
63
WEN
A2
43
Flags
CZERO
K4
65
Coefficient Zero.
The registered CZERO flag of a horizontal
dimension TMC2301 goes HIGH if X < 0, XMIN
≤
X
≤
XMAX, or
X
≥
4096 (1000 hex). It goes LOW if 0
≤
X
≤
XMIN or XMAX < X <
4096. The logical AND of the CZERO flags of a two-dimensional
pair of TMC2301s will go LOW when the source address falls
outside a rectangle with vertices (XMIN, YMIN), (XMAX, YMIN),
(XMIN, YMAX), and (XMAX, YMAX), denoting an invalid address.
The external data path can be wired to substitute a selected
background value whenever this AND = 0.
End of Transform.
In the standard two-device system, a row
sequencer DONE flag HIGH after the last walk at the end of the
last row of an image (during UWRI LOW) indicates the end of the
transform. This registered output is usually ignored on the column
device. See the Transformation Control Parameters, AUTOINIT.
End of Row/Page.
The registered END flag goes HIGH during
the last pixel of the last walk in a row in the case of the row chip,
and the last pixel of the last walk in a column in the column chip,
in the two-device architecture. This output is used as the end-of-
line and end-of-frame indicator in conjunction with the INTER
inputs of both TMC2301s.
DONE
D2
48
END
C1
47
Pin Descriptions
(continued)
Pin Name
Pin Number
PGA
Pin Function Description
PLCC
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMC2302A | Image Manipulation Sequencer |
| TMC2302AH5C | Image Manipulation Sequencer |
| TMC2302AH5C1 | Image Manipulation Sequencer |
| TMC2302AKEC | Image Manipulation Sequencer |
| TMC2302AKEC1 | Image Manipulation Sequencer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302A | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AH5C | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AH5C1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AKEC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
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