參數(shù)資料
型號(hào)： TMC2302AKEC1
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 數(shù)字信號(hào)處理外設(shè)
英文描述： Image Manipulation Sequencer
中文描述： 16-BIT, DSP-ADDRESS SEQUENCER, PQFP120
封裝： METRIC, QFP-120
文件頁(yè)數(shù)： 1/36頁(yè)
文件大?。?/td> 188K
代理商： TMC2302AKEC1
P
www.fairchildsemi.com
Features
Asynchronous loading of control parameters
Rapid (25ns per pixel) rotation, warping, panning, and
scaling of images
Three-dimensional image addressing capability
General third-order polynomial transformations in two
dimensions on-chip
Three-dimensional transformation of up to order 1.5 also
supported
Flexible, user-configurable pixel datapath timing structure
Static convolutional filtering of up to 16 x 16 Pixel (one-
pass), 256 x 256 pixel (two-pass) or 256 x 256 x 256 pixel
(three-pass) windows
User-selectable source image subpixel resolution of
2
to 2
Pin-compatible upgrade to TMC2302
24-bit (optional 36-bit) positioning precision within the
source image space, 48-bit internal precision
Low power CMOS process
Available in a 120-pin Plastic Pin Grid Array and 120-lead
Metric Quad Flat Pack
-8
-16
Applications
High-performance video special-effects generators
Guidance systems
Image recognition
Robotics
High-precision image registration
Description
The TMC2302A, a pin-compatible replacement for the
TMC2302, is a high-speed self-sequencing address genera-
tor which supports image manipulations such as rotation,
rescaling, warping, filtering, and resampling. It remaps the
pixel locations of a target (display) space back into those of a
source image space. The degree and type of image manipula-
tion is determined by the remapping selected.
To remap from the target to the source space, this integrated
circuit computes a series of polynomials of the target space
coordinates, based on user-assigned coefficients. Two
TMC2302A chips can generate third-order warps of a two-
dimensional image, whereas three can second-order warp a
three-dimensional image.
Simplified Block Diagram
65-2302-01
ASYNCHRONOUS
HOST INTERFACE
IDAT
15-0
IADR
6-0
ICS
IWR
CONTROL
PARAMETER
REGISTERS
CONTROL
NOOP
SYNCHRONOUS
HOST INTERFACE
INIT
SYNC
CLK
TARGET
ADDRESS
GENERATOR
SOURCE
ADDRESS
GENERATOR
SOURCE MEMORY
INTERFACE
CONVOLUTIONAL
CONTROL
TARGET
MEMORY
INTERFACE
SYNC FLAGS
OES
SADR
23-0
SVAL
OEK
ACC
TWR
KADR
7-0
OET
TVAL
TADR
11-0
END
DONE
WALK
COUNTER
T MC2302A
Image Manipulation S equenc er
40 MHz
Rev. 0.9.2
相關(guān)PDF資料
PDF描述
TMC2330AH5C Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330AH5C1 Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330A Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330AG1C Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330AG1C1 Coordinate Transformer 16 x 16 Bit, 40 MOPS
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
TMC2330A 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330AG1C 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330AG1C1 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330AH5C 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS
TMC2330AH5C1 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Coordinate Transformer 16 x 16 Bit, 40 MOPS
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*