參數資料
型號： TMC2301
廠商： Fairchild Semiconductor Corporation
英文描述： 15, 18, 20 MHz Image Resampling Sequencer(15, 18, 20 MHz圖像再采樣序列發(fā)生器)
中文描述： 15，18，20 MHz的圖像重采樣音序器（15，18，20 MHz的圖像再采樣序列發(fā)生器）
文件頁數： 19/26頁
文件大小： 237K
代理商： TMC2301
PRODUCT SPECIFICATION
TMC2301
19
Application Note
Nearest Neighbor Operation—Additional
Timing Details
Example A, PIPE = 0
Inspecting Figure 13:
PIPE = 0, KER = 0 (near neighbor), AUTOIN = 1 (on),
UMN = 0, UMX = 5, VMN = 0, VMX = 5,
DX/DU = 1, DY/DV = 1, XO = 0
First rising edge of CLK after INIT falling edge is #0.
Table entries are events after listed clock rising edge.
END, DONE flags = 0, except where shown as 1.
UWRI goes low and remains low with CLK #2.
Example B, PIPE = 1
Now, referring to Figure 14:
PIPE = 1, KER = 0 (near neighbor), AUTOIN = 1 (on),
UMN = 0, UMX = 5,VMN = 0,VMX=5,
DX/DU = 1, DY/DV = 1, XO = 0
First rising edge of CLK after INIT falling edge is #0.
Table entries are events after listed clock rising edges.
END, DONE, flags = 0, except where shown as 1.
UWRI goes low with CLK #3, stays low. Otherwise, the tim-
ing is the same as Figure 13, i.e., pipeline delays UWRI and
ACC by one clock cycle.
Bilinear Interpolation
Example C, PIPE = 0
From Figure 15, we can see the following:
PIPE = 0, KER = 1 (bilinear), AUTOIN = 1 (on),
UMN = 0,UMX = 5,VMN = 0,VMX=5,
DX/DU = 1, DY/DV = 1, YO = 0, XO = 0
First rising edge of CLK after INIT falling edge is #0.
Table entries are events after listed clock rising edges.
END, DONE flags = 0, except where shown as 1.
CLK X
U
V
END
DON
Comments
R
C
0
0
0
First clock after INIT falling edge
1
0
0
2
0
0
0
First valid X addresses = XO
3
1
0
0
0
0
Second X; first valid U, V = UMN,
VMN
4
2
1
0
0
0
5
3
2
0
1
0
END ROW flag 3 cycles before
last X
6
4
3
0
0
0
7
5
4
0
0
0
8
6
5
0
0
0
Last X of first row
9
0
6
0
0
0
Last U, V or first row; first X of 2nd
row
10
1
0
1
0
0
First U, V of second row
11
2
1
1
0
0
12
3
2
1
1
0
END ROW flag 4 cycles before
last U, V
13
4
3
1
0
0
14
5
4
1
0
0
15
6
5
1
0
0
Last X of second row
16
0
6
1
0
0
Last U, V of second row
U = UMX + 1
35
5
4
4
0
1
END COL goes high before last X
36
6
5
4
0
1
Last X of V = VMX –1 row
37
0
6
4
0
1
First X of Last (V = VMX) row
38
1
0
5
0
1
First U, V = UMN, VMX of last now
39
2
1
5
0
1
40
3
2
5
1
1
Last END ROW flag of frame
41
4
3
5
0
1
END COL goes low when DONE
goes high
42
5
4
5
0
0
1
DONE immediately before last X
43
6
5
5
0
0
Last X of frame
44
0
6
5
0
0
Last U, V = UMX + 1, VMX
45
1
0
0
0
0
First U, V = UMN, VMN of new
frame
46
2
1
0
0
0
47
3
2
0
1
0
First END ROW flag of new frame
CLK X
U
V
END
ROW UWR ACC DON
Comments
0
1
0
1st CLK after INIT
falling edge
1
0
0
2
0
1
0
1st valid X address =
XO: start 1st ACCum
3
1
0
1
4
1
1
1
5
0
1
1
End 1st 2x2 kernel;
end 1st ACCum
6
1
0
0
1
0
1st valid u, v = UMN,
VMN; 2nd ACCum
start
7
2
0
0
0
1
8
2
0
0
1
1
9
1
0
0
1
1
10
2
1
0
1
0
2nd valid u, v =
UMN + 1, VMN
11
3
1
0
0
1
12
3
1
0
1
1
13
2
1
0
1
1
14
3
2
0
1
0
3rd valid u, v =
UMN + 2, VMN
15
4
2
0
0
1
16
4
2
0
1
1
17
3
2
0
1
1
End 4th 2x2 kernel
160
5
3
5
1
1
1
161
4
3
5
1
1
1
162
5
4
5
1
1
0
Begin next-to-last
x-walk
163
6
5
4
1
0
1
164
6
5
4
1
1
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