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參數(shù)資料
| 型號： | TMC2301 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 15, 18, 20 MHz Image Resampling Sequencer(15, 18, 20 MHz圖像再采樣序列發(fā)生器) |
| 中文描述： | 15，18，20 MHz的圖像重采樣音序器（15，18，20 MHz的圖像再采樣序列發(fā)生器） |
| 文件頁數(shù)： | 20/26頁 |
| 文件大小： | 237K |
| 代理商： | TMC2301 |
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TMC2301
PRODUCT SPECIFICATION
20
Performing Larger Interpolation Kernels
With PIPE = 0, AUTOINIT = 1, and the following
definitions:
T
xdone
= Clock cycle of final X address of a transform.
T
xend
= Clock cycle of final X address along a row.
KER = (K + 1)(K + 1), where K is the value in the “kernel
size" parameter register.
The following relationships hold true:
First X address
valid 3 rising clock edges after INlTs
failing edge.
END FLAG
goes HIGH for KER cycles at clock cycle
T
xend
– 1 – 2*KER. Otherwise stated,
END is active for one walkaround starting
two walkarounds and one cycle prior to the
final source address of a row.
DONE FLAG
goes HIGH for one cycle at clock cycle
T
xdone
– 1. Otherwise stated, DONE is
active for one clock cycle one cycle prior
to the last source address of the final
walkaround.
165
5
4
5
1
1
166 6
5
5
1
0
Begin last x-walk
167
7
5
5
0
1
168
7
5
5
1
1
1
169
6
5
5
1
1
Last x of frame
170
0
6
5
1
0
171
1
6
5
0
1
172
1
6
5
1
1
173
0
6
5
1
1
Last u, v = UMX + 1,
VMX
174
1
0
0
1
0
First u, v of new
frame
175
2
0
0
0
1
176
2
0
0
1
1
177
1
0
0
1
1
CLK X
U
V
END
ROW UWR ACC DON
Comments
Example D, KER = 0 (nearest neighbor), UMIN = 0,
UMAX = 3, UMIN = 0, VMAX = 2
If first CLOCK edge after INIT goes low is 0, then:
First x, y out (= XO, YO) appears after CLOCK edge 2.
First u, v out (= 0, 0) appears after CLOCK edge 3.
END is high after CLOCK edge 13 only.
DONE is high after CLOCK edge 16.
Last x out appears after CLOCK edge 16.
Last u, v out (= 4, 2) appears after CLOCK edge 17.
Example E, KER = 1, (1 pass bilinear), UMIN = 0,
UMAX = 4, VMIN = 1,VMAX = 3
If first CLOCK edge after INIT goes low is 0, then:
First x, y out (= XO, YO) appears after CLOCK edge 2.
First u, v out (= 0, 1) appears after CLOCK edge 6 and
remains through edges 7, 8 and 9.
END is high after CLOCK edge 92, goes low after 96.
DONE is high after CLOCK edge 100 only.
Last x out appears CLOCK edge 101.
Last u, v out (= 5, 3) appears after CLOCK edge 102 and
remains through edges 103, 104 and 105.
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| TMC2302A | Image Manipulation Sequencer |
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| TMC2302AH5C1 | Image Manipulation Sequencer |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2302A | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AH5C | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AH5C1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AKEC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
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