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參數資料
| 型號： | TMC2301 |
| 廠商： | Fairchild Semiconductor Corporation |
| 英文描述： | 15, 18, 20 MHz Image Resampling Sequencer(15, 18, 20 MHz圖像再采樣序列發(fā)生器) |
| 中文描述： | 15，18，20 MHz的圖像重采樣音序器（15，18，20 MHz的圖像再采樣序列發(fā)生器） |
| 文件頁數： | 15/26頁 |
| 文件大?。?/td> | 237K |
| 代理商： | TMC2301 |
PRODUCT SPECIFICATION
TMC2301
15
Applications Discussion
Basic Operation
Each TMC2301 pair contains address controllers which exe-
cute patterns much like the following FORTRAN 3-level
nested DO loop:
1.
The inner loop is a clockwise outgoing spiral "walk"
through the N-element coefficient kernel.
2.
The middle loop is a left-to-right "scan" along each row
of the output image space.
3.
Finally, the outer loop is a top-to-bottom "scan" down
each column of the output image space.
A typical one pass image transformation proceeds as
follows:
1.
The device pair outputs the addresses (X
0
, Y
0
), which is
the first point in the source image, and (CAX, CAY), the
interpolation lookup table address for the first pixel in
the kernel. The output ACC goes LOW, causing the
external accumulator to load the first product without
summation, clearing the accumulator.
2.
For the next N cycles, the IRS walks through an outward
clockwise spiral in (x, y) space, accumulating pixel-
interpolation coefficient products. The spiral sequence is
depicted in Figure 8.
3.
After the completion of the first spiral walk, the IRS out-
puts the target address of the first pixel, (UMIN, VMIN)
and the control UWRI, along with the initial (X, Y) val-
ues of the next spiral walk. ACC and UWRI can be
delayed by one clock cycle by setting the control bit
PIPE to 1 (HIGH) simplifying the task of interfacing the
TMC2301 to buffered source image memory.
4.
After the last cycle of the next spiral, UWRI again goes
LOW for one clock, and the target address outputs are
updated, pointing to the location of the pixel calculation
just completed, (UMIN + 1, VMIN).
5.
The third spiral walk begins with ACC going LOW, and
ends with (UMIN + 2, VMIN) output and UWRI going
LOW.
Figure 8. Timing Diagram and Pixel Map Showing Outward Clockwise Spiral Walk
Generated by TMC2301 (2x2 Kernel Shown)
CLK
65-2301-13
X, Y
11-0
CA
7-0
U, V
11-0
ACC
PIPE = 0
UWRI
ACC
UWRI
NEXT WALK
NEW U, V
PIPE = 1
Notes:
1. Assumes that OETA is LOW and NOOP is HIGH.
2. Timing parameters are not shown on this diagram.
相關PDF資料 |
PDF描述 |
|---|---|
| TMC2302A | Image Manipulation Sequencer |
| TMC2302AH5C | Image Manipulation Sequencer |
| TMC2302AH5C1 | Image Manipulation Sequencer |
| TMC2302AKEC | Image Manipulation Sequencer |
| TMC2302AKEC1 | Image Manipulation Sequencer |
相關代理商/技術參數 |
參數描述 |
|---|---|
| TMC2302A | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AH5C | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AH5C1 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Fairchild Semiconductor Corporation 功能描述: |
| TMC2302AKEC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
| TMC2302AKEC1 | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Image Manipulation Sequencer |
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