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參數(shù)資料
| 型號： | TLFD600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GT 4C 2#8 2#16 PIN RECP WALL |
| 中文描述： | 寬帶編解碼器帶有集成線路驅動器和接收 |
| 文件頁數(shù)： | 5/36頁 |
| 文件大小： | 502K |
| 代理商： | TLFD600 |
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TLFD600
ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER
SLAS280B
–
MAY 2000
–
REVISED NOVEMBER 2000
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
I/O
DESCRIPTION
NAME
NO.
MODESEL
10
I
Mode selection. MODESEL = 0 enable full rate mode. MODESEL = 1 enable G.lite mode. The default
state of this pin is low. The chip goes with the setting of the register programming, if the configuration
is different with this pin.
PLLSEL
26
I
DPLL mode selection. PLLSEL = 1 will enable DPLL mode. The default state of this pin is low.
PWRDWN
11
I
Power-down pin. When PWRDWN is pulled low, the device goes into power-down mode.
Voltage reference filter negative output. There are two capacitors, with values of 10
μ
F and 0.1
μ
F,
connected in parallel to analog ground. The nominal dc voltage at this terminal is 0.5 V.
REFM
41
O
REFP
42
O
Voltage reference filter positive output. There are two capacitors, with values of 10
μ
F and 0.1
μ
F,
connected in parallel to analog ground. The dc voltage at this terminal is 2.5 V.
RESET
12
I
Device reset input pin. Initializes all of the device
’
s internal registers to their default values when
RESET is pulled low.
RXBANDGAP
43
O
RX channel bandgap filter node. This terminal is provided for decoupling of the 1.5-V band gap
reference. There are two capacitors, with values of 10
μ
F and 0.1
μ
F, connected in parallel to analog
ground. This node should not be used as a voltage source.
RXINM
56
I
RX channel stage negative input. This pin should not be directly connected. Refer to
receive channel
for configuration.
RXINP
55
I
RX channel stage positive input. This pin should not be directly connected. Refer to
receive channel
for configuration.
SCLK
13
O
Serial port shift clock (for both transmit and receive)
SDR
14
I
Serial data receive
SDX
17
O
Serial data transmit
TXBANDGAP
7
O
TX channel band gap filter node. This terminal is provided for decoupling of the 1.5-V band gap
reference. There are two capacitors, with values of 10
μ
F and 0.1
μ
F, connected in parallel to analog
ground. This node should not be used as a voltage source.
TXOUTP
3
O
TX channel positive output
TXOUTM
4
O
TX channel negative output
VCXO_CNTL
47
O
DAC output to control off-chip VCXO
Decoupling VMID for ADC. Add a 10-
μ
F and a 0.1-
μ
F capacitor between this pin and analog ground.
Substrate. Connect to analog ground
VMID_ADC
40
O
VSS
detailed description
48
I
transmit channel
The transmitter channel is powered by a high performance DAC. This is a 4.416 MHz, 14-bit DAC that provides
16X over-sampling to reduce the DAC noise. A band pass filter limits the output of the transmitter from 28.875
kHz to 138 kHz. A programmable attenuation with a range of 24 dB, in 1 dB step size, drives the output into the
on-chip ADSL line driver (ac-coupling is needed). The 25.875-kHz digital high pass filter (HPF) can be bypassed
by register programming.
The interface transfer rate is either 276 kHz or 552 kHz, controlled by register programming. The 138-kHz low
pass filter edge is programmable and is controlled by bit D4 of FMR register. D4=0 selects 138-kHz (
±
3.5%)
pole, while D4=1 selects a 125-kHz (
±
3.5%) pole. For details of register programming, see register
programming section.
The output spectrum of the DAC complies with the nonoverlapped PSD mask specified in the ITU standard
G.992.2 for G.lite application and G.992.1 for full rate application.
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