參數(shù)資料
型號(hào)： TLFD600
廠商： Texas Instruments, Inc.
英文描述： GT 4C 2#8 2#16 PIN RECP WALL
中文描述： 寬帶編解碼器帶有集成線路驅(qū)動(dòng)器和接收
文件頁(yè)數(shù)： 16/36頁(yè)
文件大?。?/td> 502K
代理商： TLFD600
TLFD600
ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER
SLAS280B
–
MAY 2000
–
REVISED NOVEMBER 2000
16
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
DPLL description (continued)
The position of the first jittering SCLK cycle is calculated by using the following equation:
(NCO_DIV_DLY [7 : 0]
1)
16
7
The following jittering SCLKs will separate by 16 SCLK from the first one if NCO_DELTA[3:0] is more than one.
Figures 16 and 17 shows the timing of SCLK at the following setting:
NCO_DELTA [7:4] =
–
1
NCO_DELTA [3:0] = 2
NCO_DIV_DELAY = 2
64 SCLKs
16 SCLKs
P
P
P
FSR
FSX
SDR
SCLK
Data
P
P
P
P
P
P
P
P
P
Data
Don
’
t care
Don
’
t care
S
P
The 9th SCLK duty cycle change
to 14ns(1) and 7ns(0)
15th
0
Secondary Command Request
Command to Program
NCO_DIV_DELAY
Start counting
Figure 16. DPLL Operation Example (FSR = 552 kHz and FSX = 2208 kHz)
NOTE: The situation will be the same for FSR = 276 kHz
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