
TLFD600
ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER
SLAS280B
–
MAY 2000
–
REVISED NOVEMBER 2000
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PROGRAMMING INFORMATION
GPR-D
–
GPIO data register
Address: 01001b
Contents at reset: 00000000b
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reserved
GPOD[5]
GPOD[4]
GPOD[3]
GPOD[2]
GPOD[1]
GPOD[0]
Table 10. GPIO Control Table
BIT NAME
D7
D6
D5
D4
D3
D2
D1
D0
Description
Reserved
0
Reserved
Reserved
0
Reserved
GPOD[5]
0/1
GPO5 = 0/1
GPOD[4]
0/1
GPO4 = 0/1
GPOD[3]
0/1
GPO3 = 0/1
GPOD[2]
0/1
GPO2 = 0/1
GPIOD[1]
0/1
GPIO1 = 0/1 when GPIO1 is configured as output. See
Note 7.
GPIOD[0]
0/1
GPIO0 = 0/1 when GPIO1 is configured as output. See
Note 7.
NOTE 7: It is recommended to write zeroes to GPIO1 and GPIO0 if they are configured as inputs.
FMR
–
frequency mode register
Address: 01010b
Contents at reset: 00000000b
D7
D6
D5
D4
D3
D2
D1
D0
Reserved
Reserved
Reserved
SLTXBW
Reserved
SLRXBW
DBLTXS
TOGMOD
Table 11. FMR Control Table
BIT NAME
D7
D6
D5
D4
D3
D2
D1
D0
DESCRIPTION
Reserved
0
Reserved
Reserved
0
Reserved
Reserved
0
Reserved
SLTXBW
1
TX LPF bandwidth 125 kHz
SLTXBW
0
TX LPF bandwidth 138 kHz
Reserved
0
Reserved
SLRXBW
0
Reserved
DBLTXS
1
TX FSR sampling at 552 Ksps
DBLTXS
0
TX FSR sampling at 276 Ksps
TOGMOD
1
Work mode (G.lite/full rate) opposite of that selected by
MODESEL pin
TOGMOD
NOTE 8: Table 12 shows the effect of MODESEL pin (pin 10) and TOGMOD bit (FMR[0]).
0
Work mode (G.lite/full rate) as selected by MODESEL pin