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參數(shù)資料
| 型號： | TLFD600 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | GT 4C 2#8 2#16 PIN RECP WALL |
| 中文描述： | 寬帶編解碼器帶有集成線路驅(qū)動器和接收 |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 502K |
| 代理商： | TLFD600 |
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TLFD600
ADSL CODEC WITH INTEGRATED LINE DRIVER AND RECEIVER
SLAS280B
–
MAY 2000
–
REVISED NOVEMBER 2000
4
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
I/O
DESCRIPTION
NAME
NO.
AMP1INM
AMP2INM
50
59
I
Auxiliary amplifier 1 and 2 negative input
AMP1INP
AMP2INP
51
58
I
Auxiliary amplifier 1 and 2 positive input
AMP1OUTM
AMP2OUTM
52
57
O
Auxiliary amplifier 1 and 2 negative output
AMP1OUTP
AMP2OUTP
49
60
O
Auxiliary amplifier 1 and 2 positive output
ANA_TST
46
I
External resistor connection input. A 15-k
(
±
5%) resistor must be connected between
ANA_TST and analog ground.
AVDD_DRIVER
63
I
Analog power supply for TX driver (12 V)
AVDD_REF
45
I
Reference analog supply
AVDD_RX
38, 53
I
RX channel filter analog supply
AVDD_TX
5
I
TX channel analog supply
AVSS_DRIVER
61
I
TX driver analog supply return (analog ground)
AVSS_REF
44
I
Reference analog supply return (analog ground)
AVSS_RX
39, 54
I
RX channel filter analog supply return (analog ground)
AVSS_TX
6
I
TX channel analog supply return (analog ground).
CLK1OUT
27
O
Generates clock of frequency MCLKx4/n, where n is 7 or 9. Value of n is selected by CLK1SEL.
CLK2OUT
28
O
Generates clock of frequency MCLKx4/34.5.
CLK1SEL
20
I
Selects whether n = 7 or 9 for CLK1OUT. For CLK1SEL = 0, n = 6.
CLKOUT_EN
21
I
Enable CLK1OUT and CLK2OUT when CLKOUT_EN is high. The default state of
CLKOUT_EN is low.
COMPDAC1
8
I
TX channel decoupling cap input A. Add a 1-
μ
F ceramic capacitor to analog power supply.
TX channel decoupling cap input B. Add a 1-
μ
F ceramic capacitor to analog power supply.
TX channel driver negative input. A 0.1-
μ
F capacitor is needed when it connects to TXOUTM.
TX channel driver positive input. A 0.1-
μ
F capacitor is needed when it connects to TXOUTP.
TX channel driver negative output
COMPDAC2
9
I
DRIVERINM
2
I
DRIVERINP
1
I
DRIVEROUTM
62
O
DRIVEROUTP
64
O
TX channel driver positive output
DVDD
DVDD_IO
22
I
Digital power supply
18
I
Power supply for digital I/O buffer
DVDD_RX
30
I
RX channel digital power supply
DVSS
DVSS_IO
23, 24, 37
I
Digital ground
19
I
Digital I/O buffer supply return (digital ground)
DVSS_RX
31
I
RX channel digital supply return (digital ground)
FSX
16
O
Serial port frame sync transmit signal
FSR
15
O
Serial port frame sync receive signal
GPIO0
GPIO1
29
32
I/O
General-purpose I/O
GPO2
–
5
33
–
36
O
General-purpose output
MCLKIN/PLLCLKIN
25
I
Master clock input for normal mode (use off-chip VCXO) and DPLL (use fix input clock and
change clock phase by control register) mode. The required input clock frequency is
35.328 MHz
±
50 ppm.
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