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TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A
–
AUGUST 2001
–
REVISED JULY 2003
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
FN
NO.
PN
NO.
I/O
DESCRIPTION
A0
A1
A2
34
33
32
48
47
46
I
Register select terminals. A0, A1, and A2 are three inputs used during read and write operations to
select the ACE register to read or write.
CSA, CSB,
CSC, CSD
16, 20,
50, 54
28, 33,
68, 73
I
Chip select. Each chip select (CSx) enables read and write operations to its respective channel.
CTSA, CTSB,
CTSC, CTSD
11, 25,
45, 59
23, 38,
63, 78
I
Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS)
of the modem-status register. Bit 0 (
CTS) of the modem-status register indicates that CTS has
changed state since the last read from the modem-status register. If the modem-status interrupt is
enabled when CTS changes levels and the auto-CTS mode is not enabled, an interrupt is generated.
CTS is also used in the auto-CTS mode to control the transmitter.
D7
–
D0
66
–
68
1
–
5
15
–
11,
9
–
7
I/O
Data bus. Eight data lines with 3-state outputs provide a bidirectional path for data, control, and status
information between the TL16C554A and the CPU. D0 is the least-significant bit (LSB).
DCDA, DCDB,
DCDC, DCDD
9, 27,
43, 61
19,42,
59, 2
I
Data carrier detect. A low on DCDx indicates the carrier has been detected by the modem. The
condition of this signal is checked by reading bit 7 of the modem-status register.
DSRA, DSRB,
DSRC, DSRD
10, 26,
44, 60
22, 39,
62, 79
I
Data set ready. DSRx is a modem-status signal. Its condition can be checked by reading bit 5 (DSR)
of the modem-status register. DSR has no effect on the transmit or receive operation.
DTRA, DTRB,
DTRC, DTRD
12, 24,
46, 58
24, 37,
64, 77
O
Data terminal ready. DTRx is an output that indicates to a modem or data set that the ACE is ready
to establish communications. It is placed in the active state by setting the DTR bit of the modem-
control register. DTRx is placed in the inactive state (high) either as a result of the master reset during
loop-mode operation, or when clearing bit 0 (DTR) of the modem-control register.
GND
6, 23,
40, 57
16, 36,
56, 76
Signal and power ground
INTN
65
6
I
Interrupt normal. INTN operates in conjunction with bit 3 of the modem-status register and affects
operation of the interrupts (INTA, INTB, INTC, and INTD) for the four universal asynchronous
receiver/transceivers (UARTs) per the following table.
INTN
OPERATION OF INTERRUPTS
Brought low or
allowed to float
Interrupts are enabled according to the state of OUT2 (MCR bit 3). When the MCR
bit 3 is cleared, the 3-state interrupt output of that UART is in the high-impedance
state. When the MCR bit 3 is set, the interrupt output of the UART is enabled.
Brought high
Interrupts are always enabled, overriding the OUT2 enables.
INTA, INTB,
INTC, INTD
15, 21,
49, 55
27, 34,
67, 74
O
External interrupt output. The INTx outputs go high (when enabled by the interrupt register) and
inform the CPU that the ACE has an interrupt to be serviced. Four conditions that cause an interrupt
to be issued are: receiver error, receiver data available or timeout (FIFO mode only), transmitter
holding register empty, and an enabled modem-status interrupt. The interrupt is disabled when it is
serviced or as the result of a master reset.
IOR
52
70
I
Read strobe. A low level on IOR transfers the contents of the selected register to the external CPU
bus.
IOW
18
31
I
Write strobe. IOW allows the the CPU to write to the register selected by the address.
RESET
37
53
I
Master reset. When active, RESET clears most ACE registers and sets the state of various signals.
The transmitter output and the receiver input are disabled during reset time.
RIA, RIB,
RIC, RID
8, 28,
42, 62
18, 43,
58, 3
I
Ring detect indicator. A low on RIx indicates the modem has received a ring signal from the telephone
line. The condition of this signal can be checked by reading bit 6 of the modem-status register.
RTSA, RTSB,
RTSC, RTSD
14, 22,
48, 56
26, 35,
66, 75
O
Request to send. When active, RTS informs the modem or data set that the ACE is ready to receive
data. RTS is set to the active level by setting the RTS modem-control register bit, and is set to the
inactive (high) level either as a result of a master reset, or during loop-mode operations, or by clearing
bit 1 (RTS) of the MCR. In the auto-RTS mode, RTS is set to the inactive level by the receiver
threshold-control logic.