參數(shù)資料
型號(hào): TL16C554AI
廠商: Texas Instruments, Inc.
英文描述: ASYNCHRONOUS-COMMUNICATIONS ELEMENT
中文描述: 異步通信元
文件頁(yè)數(shù): 33/40頁(yè)
文件大?。?/td> 605K
代理商: TL16C554AI
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A
AUGUST 2001
REVISED JULY 2003
33
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
auto-CTS and auto-RTS functional timing
Start
Bits 0
7
Start
Bits 0
7
Start
Bits 0
7
Stop
Stop
Stop
SOUT
CTS
NOTES: A. When CTS is low, the transmitter keeps sending serial data out.
B. If CTS goes high before the middle of the last stop bit of the current byte, the transmitter finishes sending the current byte but it does
not send the next byte.
C. When CTS goes from high to low, the transmitter begins sending data again.
Figure 21. CTS Functional Timing Waveforms
The receiver FIFO trigger level can be set to 1, 4, 8, or 14 bytes. These are described in Figures 3 and 4.
Start
Byte N
Start
Byte N+1
Start
Byte
Stop
Stop
Stop
SIN
RTS
RD
(RD RBR)
1
2
N
N+1
NOTES: A. N = RCV FIFO trigger level (1, 4, or 8 bytes)
B. The two blocks in dashed lines cover the case where an additional byte is sent as described in the preceding auto-RTS section.
Figure 22. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 1, 4, or 8 Bytes
Byte 14
Byte 15
SIN
RTS
RD
(RD RBR)
NOTES: A. RTS is deasserted when the receiver receives the first data bit of the sixteenth byte. The receive FIFO is full after finishing the
sixteenth byte.
B. RTS is asserted again when there is at least one byte of space available and no incoming byte is in processing or there is more than
one byte of space available.
C. When the receive FIFO is full, the first receive buffer register read reasserts RTS.
Start
Byte 18
Stop
Start
Byte 16
Stop
RTS Released After the
First Data Bit of Byte 16
Figure 23. RTS Functional Timing Waveforms, RCV FIFO Trigger Level = 14 Bytes
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