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參數(shù)資料
| 型號(hào)： | TL16C554AI |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | ASYNCHRONOUS-COMMUNICATIONS ELEMENT |
| 中文描述： | 異步通信元 |
| 文件頁數(shù)： | 20/40頁 |
| 文件大?。?/td> | 605K |
| 代理商： | TL16C554AI |
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TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A
–
AUGUST 2001
–
REVISED JULY 2003
20
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
FIFO-control register (FCR)
The FCR is a write-only register at the same location as the IIR. It enables the FIFOs, sets the trigger level of
the receiver FIFO, and selects the type of DMA signalling.
Bit 0: FCR0 enables the transmit and receive FIFOs. All bytes in both FIFOs can be cleared by clearing
FCR0. Data is cleared automatically from the FIFOs when changing from the FIFO mode to the TL16C450
mode (see FCR bit 0) and vice versa. Programming of other FCR bits is enabled by setting FCR0.
Bit 1: When set, FCR1 clears all bytes in the receiver FIFO and resets its counter. This does not clear the
shift register.
Bit 2: When set, FCR2 clears all bytes in the transmit FIFO and resets the counter. This does not clear the
shift register.
Bit 3: When set, FCR3 changes RXRDY and TXRDY from mode 0 to mode 1 if FCR0 is set.
Bits 4 and 5: FCR4 and FCR5 are reserved for future use.
Bits 6 and 7: FCR6 and FCR7 set the trigger level for the receiver FIFO interrupt and the auto-RTS flow
control (see Table 4).
Table 4. Receiver FIFO Trigger Level
BIT
RECEIVER FIFO
TRIGGER LEVEL (BYTES)
7
6
0
0
01
0
1
04
1
0
08
1
1
14
FIFO interrupt mode operation
The following receiver status occurs when the receiver FIFO and the receiver interrupts are enabled:
1.
LSR0 is set when a character is transferred from the shift register to the receiver FIFO. When the FIFO is
empty, it is reset.
2.
IIR = 06 receiver line status interrupt has higher priority than the receive data available interrupt
IIR = 04.
3.
Receive data available interrupt is issued to the CPU when the programmed trigger level is reached by the
FIFO. As soon as the FIFO drops below its programmed trigger level, it is cleared.
4.
IIR = 04 (receive data available indicator) also occurs when the FIFO reaches its trigger level. It is cleared
when the FIFO drops below the programmed trigger level.
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| TL16C554AIFN | 功能描述:UART 接口集成電路 Quad UART w/ 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C554AIFNR | 功能描述:UART 接口集成電路 Quad UART w/ 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C554AIPN | 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C554AIPNG4 | 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| TL16C554AIPNR | 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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