參數(shù)資料
型號(hào)： TL16C554AI
廠商： Texas Instruments, Inc.
英文描述： ASYNCHRONOUS-COMMUNICATIONS ELEMENT
中文描述： 異步通信元
文件頁(yè)數(shù)： 21/40頁(yè)
文件大?。?/td> 605K
代理商： TL16C554AI
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A
–
AUGUST 2001
–
REVISED JULY 2003
21
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
FIFO interrupt mode operation (continued)
The following receiver FIFO character time-out status occurs when receiver FIFO and the receiver interrupts
are enabled.
1.
When the following conditions exist, a FIFO character time-out interrupt occurs:
a.
Minimum of one character in FIFO
b.
No new serial characters have been received for at least four character times. At 300 baud and 12-bit
characters, the FIFO time-out interrupt causes a latency of 160 ms maximum from received character
to interrupt generation.
c.
The receive FIFO has not been read for at least four character times.
2.
By using the XTAL1 input for a clock signal, the character times can be calculated. The delay is proportional
to the baud rate.
3.
The time-out timer is reset after the CPU reads the receiver FIFO or after a new character is received. This
occurs when there has been no time-out interrupt.
4.
A time-out interrupt is cleared and the timer is reset when the CPU reads a character from the receiver FIFO.
Transmit interrupts occurs as follows when the transmitter and transmit FIFO interrupts are enabled
(FCR0 = 1, IER = 1).
1.
When the transmitter FIFO is empty, the transmitter holding register interrupt (IIR = 02) occurs. The interrupt
is cleared when the transmitter holding register is written to or the IIR is read. One to sixteen characters can
be written to the transmit FIFO when servicing this interrupt.
2.
The transmitter FIFO empty indicators are delayed one character time minus the last stop-bit time whenever
the following occurs:
THRE = 1, and there have not been at least two bytes in transmit FIFO since the last THRE = 1. The first
transmitter interrupt comes immediately after changing FCR0, assuming the interrupt is enabled.
Receiver FIFO trigger level and character time-out interrupts have the same priority as the receive data
available interrupt. The transmitter holding register empty interrupt has the same priority as the transmitter FIFO
empty interrupt.
FIFO polled mode operation
When the FIFOs are enabled and all interrupts are disabled, the device is in the FIFO polled mode.
In the FIFO polled mode, there is no time-out condition indicated or trigger level reached. However, the receive
and transmit FIFOs still have the capability of holding characters. The LSR must be read to determine the ACE
status.
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TL16C554AIFNR 功能描述:UART 接口集成電路 Quad UART w/ 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C554AIPN 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C554AIPNG4 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
TL16C554AIPNR 功能描述:UART 接口集成電路 Quad UART with 16-Byte FIFOs RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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