參數(shù)資料
型號: TL16C554AI
廠商: Texas Instruments, Inc.
英文描述: ASYNCHRONOUS-COMMUNICATIONS ELEMENT
中文描述: 異步通信元
文件頁數(shù): 28/40頁
文件大?。?/td> 605K
代理商: TL16C554AI
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A
AUGUST 2001
REVISED JULY 2003
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
modem-status register (MSR) (continued)
Bit 6: MSR6 is the ring indicator (RI) bit. RI is the complement of the RIx inputs. When the channel is in the
loop mode (MCR4 is set), MSR6 reflects the value of OUT1 in the MCR.
Bit 7: MSR7 is the data carrier detect (DCD) bit. Data carrier detect indicates the status of the data carrier
detect (DCD) input. When the channel is in the loop mode (MCR4 is set), MSR7 reflects the value of OUT2
in the MCR.
Reading the MSR clears the delta modem status indicators but has no effect on the other status bits. For LSR
and MSR, the setting of status bits is inhibited during status register read operations. If a status condition is
generated during a read IOR operation, the status bit is not set until the trailing edge of the read. When a status
bit is set during a read operation and the same status condition occurs, that status bit is cleared at the trailing
edge of the read instead of being set again. In the loopback mode, CTS, DSR, RI, and DCD inputs are ignored
when modem-status interrupts are enabled; however, a modem-status interrupt can still be generated by writing
to MCR3
MCR0. Applications software should not write to the MSR.
Table 8. Modem-Status Register BIts
MSR BIT
MNEMONIC
CTS
DSR
TERI
DCD
CTS
DESCRIPTION
MSR0
Delta clear to send
MSR1
Delta data set ready
MSR2
Trailing edge of ring indicator
MSR3
Delta data carrier detect
MSR4
Clear to send
MSR5
DSR
Data set ready
MSR6
RI
Ring indicator
MSR7
DCD
Data carrier detect
programming
The serial channel of the ACE is programmed by control registers LCR, IER, DLL, DLM, MCR, and FCR. These
control words define the character length, number of stop bits, parity, baud rate, and modem interface.
While the control registers can be written in any order, the IER should be written last because it controls the
interrupt enables. Once the serial channel is programmed and operational, these registers can be updated any
time the ACE serial channel is not transmitting or receiving data.
programmable baud-rate generator
The ACE serial channel contains a programmable baud-rate generator (BRG) that divides the clock (dc to
8 MHz) by any divisor from 1 to 2
16
1. Two 8-bit divisor-latch registers store the divisor in a 16-bit binary format.
These divisor-latch registers must be loaded during initialization. A 16-bit baud counter is immediately loaded
upon loading of either of the divisor latches. This prevents long counts on initial load. The BRG can use any of
three different popular frequencies to provide standard baud rates. These frequencies are 1.8432 MHz,
3.072 MHz, 8 MHz, and 16 MHz. With these frequencies, standard bit rates from 50 kbps to 512 kbps are
available. Tables 9, 10, 11, and 12 illustrate the divisors needed to obtain standard rates using these three
frequencies. The output frequency of the baud-rate generator is 16 times the data rate [divisor # = clock + (baud
rate
×
16)]. RCLK runs at this frequency.
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