參數(shù)資料
型號(hào): TL16C554AI
廠商: Texas Instruments, Inc.
英文描述: ASYNCHRONOUS-COMMUNICATIONS ELEMENT
中文描述: 異步通信元
文件頁(yè)數(shù): 22/40頁(yè)
文件大?。?/td> 605K
代理商: TL16C554AI
TL16C554A, TL16C554AI
ASYNCHRONOUS-COMMUNICATIONS ELEMENT
SLLS509A
AUGUST 2001
REVISED JULY 2003
22
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
interrupt-enable register (IER)
The IER independently enables the four serial channel interrupt sources that activate the interrupt (INTA, B, C,
D) output. All interrupts are disabled by clearing IER0
IER3 of the IER. Interrupts are enabled by setting the
appropriate bits of the IER. Disabling the interrupt system inhibits the IIR and the active (high) interrupt output.
All other system functions operate in their normal manner, including the setting of the LSR and MSR. The
contents of the IER are shown in Table 3 and described in the following bulleted list:
Bit 0:
When IER0 is set, IER0 enables the received data available interrupt and the timeout interrupts in
the FIFO mode.
Bit 1:
When IER1 is set, the transmitter holding register empty interrupt is enabled.
Bit 2:
When IER2 is set, the receiver line status interrupt is enabled.
Bit 3:
When IER3 is set, the modem-status interrupt is enabled.
Bits 4
7: IER4
IER7. These four bits of the IER are cleared.
interrupt-identification register (IIR)
In order to minimize software overhead during data character transfers, the serial channel prioritizes interrupts
into four levels as follows:
Priority 1
Receiver line status (highest priority)
Priority 2
Receiver data ready or receiver character timeout
Priority 3
Transmitter holding register empty
Priority 4
Modem status (lowest priority)
The IIR stores information indicating that a prioritized interrupt is pending and the type of interrupt. The IIR
indicates the highest priority interrupt pending. The contents of the IIR are indicated in Table 5.
Table 5. Interrupt Control Functions
INTERRUPT
IDENTIFICATION
REGISTER
INTERRUPT SET AND RESET FUNCTIONS
BIT 3
BIT 2
BIT 1
BIT 0
PRIORITY
LEVEL
INTERRUPT TYPE
INTERRUPT SOURCE
INTERRUPT
RESET CONTROL
0
0
0
1
None
None
0
1
1
0
First
Receiver line status
OE, PE, FE, or BI
LSR read
0
1
0
0
Second
Received data available
Receiver data available or
trigger level reached
RBR read until FIFO
drops below the trigger
level
1
1
0
0
Second
Character time-out
indicator
No characters have been
removed from or input to the
receiver FIFO during the last
four character times, and there
is at least one character in it
during this time.
RBR read
0
0
1
0
Third
THRE
THRE
IIR read (if THRE is the
interrupt source), or
THR write
0
0
0
0
Fourth
Modem status
CTS, DSR, RI, or DCD
MSR read
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