
Agere Systems Inc.
99
Data Sheet
May 2001
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
Functional Description
(continued)
UTOPIA (UT) Interface Block
(continued)
Multi-PHY Support
(continued)
The ATM side sends one RxENB (TxENB) signal to channel A for the grouped channels to select a channel which
has ATM cells/packets (or room) available. An MPHY channel is selected using the following procedures.
1.The ATM layer polls the RxPA[D:A] (TxPA[D:A]) status of a channel by placing its address on the RxADDR[4:0]
(TxADDR[4:0]) lines.
2.In the following cycle, the MPHY channel gives its status by driving RxPA[D:A] (TxPA[D:A]) of channel A.
3.The ATM side selects the MPHY channel by placing the desired MPHY address on the address bus
RxADDR[4:0] (TxADDR[4:0]) during this cycle; RxENB[D:A] (TxENB[D:A]) is deasserted.
4.During the next cycle, the ATM side asserts RxENB[D:A] (TxENB[D:A]), and the selection of an MPHY channel is
made.
Only one MPHY channel at a time is selected for a cell/packet transfer when ATM drives RxENB (TxENB) for
channel A from high to low. However, another MPHY channel can be polled for its RxPA (TxPA) status while the
selected channel transfers data.
Figure 28 shows an example of the single-cycle RxPA response of each channel. In this figure, channels A, B, C,
and D have Rx addresses 00, 01, 02, and 03, respectively. RxPA[A] shows the packet availability of all four chan-
nels. Channels A and C have available packets to send, and channels B and D do not have packets to send. By
driving RxENB[A] low at clock edge 1, the ATM side selects channel A, and packet transfer is started at
clock edge 2. The master samples this data at clock edge 3. At clock edge 4, RxPA[C] shows that channel C also
has a packet to send, and this is reflected to RxPA[A] at clock edge 5. RxPA[B] and RxPA[D] show the direct status
of channels B and D, indicating that they do not have packets to send.
1
2
3
4
5-7348(F)r.2
Figure 28. RxPA Responses of a Multi-PHY for All Four Channels
(PA Response Configured for One Cycle)
5
6
7
8
9
10
11
00
P1P2
P17P18
01
1F
01
1F
02
1F
03
1F
00
1F
P3P4
P5P6
P7P8
P9P10
P11P12
P13P14
P15P16
00
01
02
03
00
R
X
CLK[A]
R
X
ADDR
R
X
DATA[A]
R
X
SOP/C[A]
R
X
EOP[A]
R
X
SZ[A]
R
X
ENB[A]
R
X
PA[C]
R
X
PA[B]
R
X
PA[A]
R
X
PA[D]
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z
HIGH Z