參數(shù)資料
型號(hào): TDAT042G51A-3BLL1
英文描述: TDAT SONET/SDH 155/622/2488 Mbits/s Data Interfaces
中文描述: TDAT的SONET / SDH 155/622/2488 Mbits /秒數(shù)據(jù)接口
文件頁(yè)數(shù): 113/310頁(yè)
文件大?。?/td> 4628K
代理商: TDAT042G51A-3BLL1
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Agere Systems Inc.
85
Data Sheet
May 2001
155/622/2488 Mbits/s Data Interface
TDAT042G5 SONET/SDH
Functional Description
(continued)
UTOPIA (UT) Interface Block
(continued)
Enhanced refers to the extensions that have been added to support packet transfers. These extensions are indica-
tions of the following: (1) an end of packet (TxEOP/RxEOP), (2) the byte on which packet ends in last word (TxSZ/
RxSZ), and (3) the signal to abort a packet early (TxERR/RxERR). An abort occurs, for example, if the check sum
at the end of a packet is bad, or the end of a packet is reached prematurely. If the receive FIFO overflows because
the master cannot process packet data fast enough, an RxERR will also be generated.
UTOPIA Loopbacks
TDAT042G5 can be placed in loopback on a channel-by-channel basis. When the TDAT042G5 is placed in far-end
loopback (FELB), data from the DE is sent to and processed by the UTOPIA interface. Instead of sending it to the
UTOPIA master, however, the data is sent to the corresponding egress channel and back to the line interface.
When the TDAT042G5 is placed in near-end loopback (NELB), data from the egress channel is transferred to the
corresponding ingress channel, instead of the DE. This data is then processed by the ingress channel and is
returned to the UTOPIA master.
UTOPIA Modes
Each UTOPIA interface mode is capable of supporting various types of traffic with different bandwidth capabilities
as summarized in Table 24. In a point-to-point operational mode, any interface can be configured independently in
any of the defined modes (e.g., channel A passes ATM cells using STS-12c, channel B passes packets, etc.).
It should be noted that the U3 or U3+ (32-bit mode) can only be supported by overloading channel A and B inter-
face pins. Only the control signals from channel A are used. The channel B size and data bits are combined with
the channel A size and data bits to form the 2-bit size and the 32-bit data words. When 32-bit mode is selected,
channels B, C, and D must be configured to be idle (so that channel B will be under the control of channel A in
32-bit mode).
Multichannel multi-PHY (MPHY) capabilities are only supported on interface A by grouping the internal FIFOs and
data paths of channels B, C, and D as needed. This operational mode is described in a later section.
Table 24. UTOPIA Traffic Types
* Maximum speed may be exceeded if nonstandard load conditions are used and the clock is sourced. See CLOCK_MODE_Rx [A
D]
(registers 0x020F, 0x0213, 0x0217, 0x021B), pages 158
159 for details.
UTOPIA Name
Interface
Width
Maximum
Speed
Aggregate
Bandwidth
Traffic Type
Maximum
Number of
Interfaces
U2
16 bits
52 MHz*
622 Mbits/s (STS-12)
ATM cells only
4
U2+
16 bits
52 MHz*
622 Mbits/s (STS-12)
ATM cells/packets
4
U3, 8-bit mode
8 bits
104 MHz
622 Mbits/s (STS-12)
ATM cells only
4
U3+, 8-bit mode
8 bits
104 MHz
622 Mbits/s (STS-12)
ATM cells/packets
4
U3, 32-bit mode
32 bits
104 MHz
2.5 Gbits/s (STS-48)
ATM cells only
1
U3+, 32-bit mode
32 bits
104 MHz
2.5 Gbits/s (STS-48)
ATM cells/packets
1
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