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參數(shù)資料
| 型號： | ST7PLU09MCTRE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 99/124頁 |
| 文件大小： | 1995K |
| 代理商： | ST7PLU09MCTRE |
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On-chip peripherals
ST7LUS5, ST7LU05, ST7LU09
10.3.3
Functional description
Analog power supply
VDDA and VSSA are the high and low level reference voltage pins. In some devices (refer to
device pin out description) they are internally connected to the VDD and VSS pins.
Conversion accuracy may therefore be impacted by voltage drops and noise in the event of
heavily loaded or badly decoupled power supply lines.
Figure 34.
ADC block diagram
Digital A/D conversion result
The conversion is monotonic, meaning that the result never decreases if the analog input
does not and never increases if the analog input does not.
If the input voltage (VAIN) is greater than VDDA (high-level voltage reference) then the
conversion result is FFh in the ADCDRH register and 03h in the ADCDRL register (without
overflow indication).
If the input voltage (VAIN) is lower than VSSA (low-level voltage reference) then the
conversion result in the ADCDRH and ADCDRL registers is 00 00h.
The A/D converter is linear and the digital result of the conversion is stored in the ADCDRH
and ADCDRL registers. The accuracy of the conversion is described in the Chapter 12:
CH2
CH1
EOC SPEED ADON
0
CH0
ADCCSR
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
AINx
ANALOG
MUX
D4
D3
D5
D9
D8
D7
D6
D2
ADCDRH
3
D1
D0
ADCDRL
00
0
SLOW
0
RADC
CADC
HOLD CONTROL
fADC
fCPU
0
1
0
DIV 2
DIV 4
SLOW
bit
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