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| 型號(hào)： | ST7PLU09MCTRE |
| 廠商： | STMICROELECTRONICS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件頁(yè)數(shù)： | 77/124頁(yè) |
| 文件大?。?/td> | 1995K |
| 代理商： | ST7PLU09MCTRE |
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I/O ports
ST7LUS5, ST7LU05, ST7LU09
9
I/O ports
9.1
Introduction
The I/O port offers different functional modes:
●
transfer of data through digital inputs and outputs
and for specific pins:
●
external interrupt generation
●
alternate signal input/output for the on-chip peripherals.
An I/O port contains up to six pins. Each pin (except PA3/RESET) can be programmed
independently as digital input (with or without interrupt generation) or digital output.
9.2
Functional description
Each port has two main registers:
●
Data Register (DR)
●
Data Direction Register (DDR)
and one optional register:
●
Option Register (OR)
Each I/O pin may be programmed using the corresponding register bits in the DDR and OR
registers, with bit X corresponding to pin X of the port. The same correspondence is used for
the DR register.
The following description takes into account the OR register (for specific ports which do not
provide this register refer to Section 9.6: I/O port implementation). The generic I/O block
diagram is shown in Figure 26.
9.2.1
Input modes
The input configuration is selected by clearing the corresponding DDR register bit.
In this case, reading the DR register returns the digital value applied to the external I/O pin.
Different input modes can be selected by software through the OR register.
Note:
1
Writing the DR register modifies the latch value but does not affect the pin status.
2
PA3 cannot be configured as input.
External interrupt function
When an I/O is configured as Input with Interrupt, an event on this I/O can generate an
external interrupt request to the CPU.
Each pin can independently generate an interrupt request. The interrupt sensitivity is
independently programmable using the sensitivity bits in the EICR register.
External interrupts are hardware interrupts. Fetching the corresponding interrupt vector
automatically clears the request latch. Changing the sensitivity of a particular external
interrupt clears this pending interrupt. This can be used to clear unwanted pending
interrupts.
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