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參數(shù)資料
| 型號： | ST7PLU09MCTRE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 26/124頁 |
| 文件大?。?/td> | 1995K |
| 代理商： | ST7PLU09MCTRE |
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ST7LUS5, ST7LU05, ST7LU09
Known limitations
121/124
15
Known limitations
15.1
Limitations in user mode (ST7LUS5 devices only)
15.1.1
Flash memory access when exiting from Halt mode
Description
When exiting from Halt mode, the CPU starts to run after 64 cycles.
However, to work properly and to be accessed safely, the Flash memory needs a delay of
42s. This problem occurs only with a CPU frequency from 2 MHz to 8 MHz (that is, with a
wake-up time from Halt mode respectively from 32s to 8s).
This limitation is NOT present in the following cases:
●
at power-on (as an additional delay of 34s is always applied)
●
for internal reset as Flash memory cells are not stopped.
Workaround
The CPU frequency must be set by software at 1 MHz before entering Halt mode.
When the CPU exits from Halt mode by an external reset, the reset pulse of at least 42s
must be applied.
15.2
Limitations in ICC mode (ST7LUS5 devices only)
These limitations can concern ICP (programming) and/or ICD (debugging) and a
workaround (when available) should be implemented in any programming or debugging tool,
as described in the following sections.
15.2.1
Spurious LVD reset after programming the option bytes
Description
When programming the LVD option from OFF to ON in ICC mode with option bytes enabled
(38-pulse mode), a spurious reset is generated and ICC communication is lost.
Workaround
At the user level, using the ICC mode with option bytes disabled (35-pulse mode), no
spurious reset is generated.
At the programming tool designer level, a spurious LVD reset can be avoided by generating
a reset after programming the option bytes.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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