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參數(shù)資料
| 型號： | ST7PLU09MCTRE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 57/124頁 |
| 文件大?。?/td> | 1995K |
| 代理商： | ST7PLU09MCTRE |
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Interrupts
ST7LUS5, ST7LU05, ST7LU09
An external interrupt triggered on edge will be latched and the interrupt request
automatically cleared upon entering the interrupt service routine.
Caution:
The type of sensitivity defined in the Miscellaneous or Interrupt register (if available) applies
to the ei source.
7.3
Peripheral interrupts
Different peripheral interrupt flags in the status register are able to cause an interrupt when
they are active if both:
●
The I bit of the CC register is cleared.
●
The corresponding enable bit is set in the control register.
If any of these two conditions is false, the interrupt is latched and thus remains pending.
An interrupt request is cleared by doing one of the following:
●
Writing ‘0’ to the corresponding bit in the status register
●
Accessing the status register while the flag is set followed by a read or write of an
associated register.
Note:
The clearing sequence resets the internal latch. A pending interrupt (that is, waiting for
being enabled) will therefore be lost if the clear sequence is executed.
Figure 13.
Interrupt processing flowchart
I BIT SET?
Y
N
IRET?
Y
N
FROM RESET
LOAD PC FROM INTERRUPT VECTOR
STACK PC, X, A, CC
SET I BIT
FETCH NEXT INSTRUCTION
EXECUTE INSTRUCTION
THIS CLEARS I BIT BY DEFAULT
RESTORE PC, X, A, CC FROM STACK
INTERRUPT
Y
N
PENDING?
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