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參數(shù)資料
| 型號： | ST7PLU09MCTRE |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PDSO8 |
| 封裝： | 0.150 INCH, ROHS COMPLIANT, PLASTIC, SOP-8 |
| 文件頁數(shù)： | 85/124頁 |
| 文件大小： | 1995K |
| 代理商： | ST7PLU09MCTRE |
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ST7LUS5, ST7LU05, ST7LU09
On-chip peripherals
63/124
Figure 28.
Lite timer block diagram
10.1.3
Functional description
The value of the 13-bit counter cannot be read or written by software. After an MCU reset, it
starts incrementing from 0 at a frequency of fOSC. A counter overflow event occurs when the
counter rolls over from 1F39h to 00h. If fOSC = 8 MHz, then the time period between two
counter overflow events is 1ms. This period can be doubled by setting the TB bit in the
LTCSR register.
When the timer overflows, the TBF bit is set by hardware and an interrupt request is
generated if the TBIE is set. The TBF bit is cleared by software reading the LTCSR register.
Watchdog
The watchdog is enabled using the WDGE bit. The normal Watchdog timeout is 2ms
(@ fOSC = 8 MHz), after which it then generates a reset.
To prevent this watchdog reset from occurring, software must set the WDGD bit. The WDGD
bit is cleared by hardware after tWDG. This means that software must write to the WDGD bit
at regular intervals to prevent a watchdog reset from occurring. Refer to Figure 29.
If the watchdog is not enabled immediately after reset, the first watchdog timeout will be
shorter than 2ms, because this period is counted starting from reset. Moreover, if a 2ms
period has already elapsed after the last MCU reset, the watchdog reset will take place as
soon as the WDGE bit is set. For these reasons, it is recommended to enable the Watchdog
LTCSR
WATCHDOG
13-bit UPCOUNTER
/2
8-bit
fLTIMER
fWDG
8 MSB
LTIC
fOSC
WDGD
WDGE
WDG
TBF
TBIE
TB
ICF
ICIE
WATCHDOG RESET
LTTB INTERRUPT REQUEST
LTIC INTERRUPT REQUEST
LTICR
INPUT CAPTURE
REGISTER
1
0
1 or 2 ms
Timebase
(@ 8 MHz
fOSC)
To 12-bit AT tImer
fLTIMER
RF
0
7
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