參數(shù)資料
型號： ST7FLITE09Y0M1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 0.150 INCH, PLASTIC, SOP-16
文件頁數(shù)： 89/111頁
文件大小： 671K
代理商： ST7FLITE09Y0M1
ST7FLITE0
79/111
OPERATING CONDITIONS (Cont’d)
13.3.4.3 Devices with ‘”6” order code suffix (tested for TA = -40 to +85°C) @ VDD = 2.7 to 3.3V
13.3.4.4 Devices with ‘”3” order code suffix (tested for TA = -40 to +125°C) @ VDD = 2.7 to 3.3V
Notes:
1. Data based on characterization results, not tested in production
2. RCCR1 is a factory-calibrated setting for 700MHz with
±0.2 accuracy @ T
A =25°C, VDD=3V. See “INTERNAL RC OS-
CILLATOR ADJUSTMENT” on page 20.
3. Guaranteed by design.
4. Averaged over a 4ms period. After the LOCKED bit is set, a period of tSTAB is required to reach ACCPLL accuracy
5. After the LOCKED bit is set ACCPLL is max. 10% until tSTAB has elapsed. See Figure 11.
Symbol
Parameter
Condit ions
Min
Typ
Max
Unit
fRC
Internal RC oscillator fre-
quency
RCCR = FF (reset value), TA=25°C, VDD= 3.0V
560
kHz
RCCR=RCCR1 2) ,TA=25°C,VDD= 3V
700
ACCRC
Accuracy of Internal RC
oscillator when calibrated
with RCCR=RCCR1 1)2)
TA=25°C,VDD=3V
-2
+2
%
TA=25°C,VDD=2.7 to 3.3V
-20
+20
%
TA=-40 to +85°C,VDD=3V
-5
10
%
IDD(RC)
RC oscillator current con-
sumption
TA=25°C,VDD=3V
7001)
A
tsu(RC)
RC oscillator setup time
TA=25°C,VDD=3V
102)
s
fPLL
x4 PLL input clock
11)
MHz
tLOCK
PLL Lock time5)
2ms
tSTAB
PLL Stabilization time5)
4ms
ACCPLL
x4 PLL Accuracy
fRC = 1MHz@TA=25°C,VDD=2.7 to 3.3V
0.14)
%
fRC = 1MHz@TA=40 to +85°C,VDD= 3V
0.14)
%
tw(JIT)
PLL jitter period
fRC = 1MHz
83)
kHz
JITPLL
PLL jitter (
f
CPU/fCPU)1
3)
%
IDD(PLL)
PLL current consumption TA=25°C190
1)
A
Symbol
Parameter
Condit ions
Min
Typ
Max
Unit
fRC
Internal RC oscillator fre-
quency
RCCR = FF (reset value), TA=25°C, VDD= 3V
560
kHz
RCCR=RCCR1 2) ,TA=25°C,VDD= 3V
700
ACCRC
Accuracy of Internal RC
oscillator when calibrated
with RCCR=RCCR1 1)2)
fRC=1MHz@TA=25°C,VDD=3V
-2
+2
%
fRC=1MHz@TA=25°C,VDD=2.7 to 3.3V
-20
+20
%
fRC=1MHz@TA=-40 to +125°C,VDD=3V
TBD
%
IDD(RC)
RC oscillator current con-
sumption
TA=25°C,VDD=3V
7001)
A
tsu(RC)
RC oscillator setup time
TA=25°C,VDD=3V
102)
s
fPLL
x4 PLL input clock
11)
MHz
tLOCK
PLL Lock time5)
2ms
tSTAB
PLL Stabilization time5)
4ms
ACCPLL
x4 PLL Accuracy
fRC = 1MHz@TA=25°C,VDD=2.7 to 3.3V
0.14)
%
fRC = 1MHz@TA=-40 to +85°C,VDD= 3V
0.14)
%
tw(JIT)
PLL jitter period
fRC = 1MHz
83)
kHz
JITPLL
PLL jitter (
f
CPU/fCPU)1
3)
%
IDD(PLL)
PLL current consumption TA=25°C190
1)
A
1
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