參數(shù)資料
型號: ST7FLITE09Y0M1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝: 0.150 INCH, PLASTIC, SOP-16
文件頁數(shù): 73/111頁
文件大?。?/td> 671K
代理商: ST7FLITE09Y0M1
ST7FLITE0
64/111
11.4 8-BIT A/D CONVERTER (ADC)
11.4.1 Introduction
The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 5 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 5 different sources.
The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.
11.4.2 Main Features
s
8-bit conversion
s
Up to 5 channels with multiplexed input
s
Linear successive approximation
s
Dual input range
– 0 to VDD or
– 0V to 250mV
s
Data register (DR) which contains the results
s
Conversion complete status flag
s
On/off bit (to reduce consumption)
s
Fixed gain operational amplifier (x8)
11.4.3 Functional Description
11.4.3.1 Analog Power Supply
The block diagram is shown in Figure 42.
VDD and VSS are the high and low level reference
voltage pins.
Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.
For more details, refer to the Electrical character-
istics section.
11.4.3.2 Input Voltage Amplifier
The input voltage can be amplified by a factor of 8
by enabling the AMPON bit in the ADAMP register.
When the amplifier is enabled, the input range is
0V to 250 mV.
For example, if VDD = 5V, then the ADC can con-
vert voltages in the range 0V to 250mV with an
ideal resolution of 2.4mV (equivalent to 11-bit res-
olution with reference to a VSS to VDD range).
For more details, refer to the Electrical character-
istics section.
Note: The amplifier is switched on by the ADON
bit in the ADCCSR register, so no additional start-
up time is required when the amplifier is selected
by the AMPON bit.
Figure 42. ADC Block Diagram
CH2
CH1
0
EOC SPEED ADON
0
CH0
ADCCSR
AIN0
AIN1
ANALOG TO DIGITAL
CONVERTER
AINx
ANALOG
MUX
RADC
CADC
D2
D1
D3
D7
D6
D5
D4
D0
ADCDR
3
fADC
HOLD CONTROL
x1 or
x8
AMPON bit
(ADCAMP Register)
fCPU
0
1
0
DIV 2
DIV 4
SLOW
bit
(ADCAMP Register)
7
0
1
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