參數(shù)資料
型號(hào)： ST7FLITE09Y0M1
廠(chǎng)商： STMICROELECTRONICS
元件分類(lèi)： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 0.150 INCH, PLASTIC, SOP-16
文件頁(yè)數(shù)： 43/111頁(yè)
文件大?。?/td> 671K
代理商： ST7FLITE09Y0M1
ST7FLITE0
37/111
10 I/O PORTS
10.1 INTRODUCTION
The I/O ports offer different functional modes:
– transfer of data through digital inputs and outputs
and for specific pins:
– external interrupt generation
– alternate signal input/output for the on-chip pe-
ripherals.
An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.
10.2 FUNCTIONAL DESCRIPTION
Each port has 2 main registers:
– Data Register (DR)
– Data Direction Register (DDR)
and one optional register:
– Option Register (OR)
Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.
The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 27
10.2.1 Input Modes
The input configuration is selected by clearing the
corresponding DDR register bit.
In this case, reading the DR register returns the
digital value applied to the external I/O pin.
Different input modes can be selected by software
through the OR register.
Note: Writing the DR register modifies the latch
value but does not affect the pin status.
External interrupt function
When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.
Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently
programmable using the sensitivity bits in the Mis-
cellaneous register.
Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt source, these
are logically ANDed. For this reason if one of the
interrupt pins is tied low, it masks the other ones.
The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when
the
corresponding
interrupt
vector
is
fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the Miscellane-
ous register must be modified.
10.2.2 Output Modes
The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.
Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.
DR register value and output pin status:
Note: When switching from input to output mode,
the DR register has to be written first to drive the
correct level on the pin as soon as the port is con-
figured as an output.
10.2.3 Alternate Functions
When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming under the following
conditions:
– When the signal is coming from an on-chip pe-
ripheral, the I/O pin is automatically configured in
output mode (push-pull or open drain according
to the peripheral).
– When the signal is going to an on-chip peripher-
al, the I/O pin must be configured in floating input
mode. In this case, the pin state is also digitally
readable by addressing the DR register.
Notes:
– Input pull-up configuration can cause unexpect-
ed value at the input of the alternate peripheral
input.
– When an on-chip peripheral use a pin as input
and output, this pin has to be configured in input
floating mode.
DR
Push-pu ll
Open-drain
0VSS
Vss
1VDD
Floating
1
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