參數(shù)資料
型號(hào)： ST7FLITE09Y0M1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 0.150 INCH, PLASTIC, SOP-16
文件頁數(shù)： 102/111頁
文件大?。?/td> 671K
代理商： ST7FLITE09Y0M1
ST7FLITE0
90/111
13.8 I/O PORT PIN CHARACTERISTICS
13.8.1 General Characteristics
Subject to general operating conditions for VDD,fOSC, and TA unless otherwise specified.
Figure 63. Two typical Applications with unused I/O Pin
Figure 64. Typical IPU vs. VDD with VIN=VSS
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5.0V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 63). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The RPU pull-up equivalent resistor is based on a resistive transistor (corresponding IPU current characteristics de-
Symbol
Parameter
Conditio ns
Min
Typ 1)
Max
Unit
VIL
Input low level voltage 2)(input
under VILmax is guaranteed to
be read as logic low)
0.3xVDD
V
VIH
Input high level voltage 2) (in-
put over VIHmin is guaranteed
to be read as logic high)
0.7xVDD
Vhys
Schmitt trigger voltage hyster-
esis 3)
400
mV
IL
Input leakage current
VSS≤VIN≤VDD
±1
A
IS
Static current consumption 4)
Floating input mode
200
RPU
Weak pull-up equivalent
resistor5)
VIN=VS
S
VDD=5V TA≤85°C
VDD=5V TA≥85°C
50
90
120
150
k
VDD=3.3V TA≤85°C
802)
130
1802)
VDD=2.7V TA≤85°C
1402)
200
2602)
CIO
I/O pin capacitance
5
pF
tf(IO)out
Output high to low level fall
time 6)
CL=50pF
Between 10% and 90%
25
ns
tr(IO)out
Output low to high level rise
time 6)
25
tw(IT)in
External interrupt pulse time 7)
1tCPU
10k
UNUSED I/O PORT
ST7XXX
10k
UNUSED I/O PORT
ST7XXX
VDD
TO BE CHARACTERIZED
1
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