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參數(shù)資料
| 型號： | ST7FLITE09Y0M1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 107/111頁 |
| 文件大小： | 671K |
| 代理商： | ST7FLITE09Y0M1 |
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ST7FLITE0
95/111
13.9 CONTROL PIN CHARACTERISTICS
13.9.1 Asynchronous RESET Pin
Subject to general operating conditions for VDD,fOSC, and TA unless otherwise specified.
Figure 71. Typical Application with RESET pin
8)9)10)
Notes:
1. Unless otherwise specified, typical data are based on TA=25°C and VDD=5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The IIO current sunk must always respect the absolute maximum rating specified in Section 13.2.2 and the sum of IIO
(I/O ports and control pins) must not exceed IVSS.
5. The RON pull-up equivalent resistor is based on a resistive transistor. Specfied for voltages on RESET pin between
VILmax and VDD
6. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
RESET pin with a duration below th(RSTL)in can be ignored.
7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environments.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).
9. Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the VIL max. level specified in section 13.9.1 on page 95 . Otherwise the reset will not be taken into account internally.
10. Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-p for example) is less than the absolute maximum value spec-
Symbol
Parameter
Conditio ns
Min
Typ 1)
Max
Unit
VIL
Input low level voltage 2) (input under VIL-
max is guaranteed to be read as logic low)
0.3xVDD
V
VIH
Input high level voltage 2) (input over
VIHmin is guaranteed to be read as logic
high)
0.7xV
DD
Vhys
Schmitt trigger voltage hysteresis 3)
2V
VOL
Output low level voltage 4)
VDD=5V
IIO=+5mA TA≤85°C
TA≥85°C
0.5
1.0
1.2
V
IIO=+2mA TA≤85°C
TA≥85°C
0.2
0.4
0.5
RON
Pull-up equivalent resistor 5)
VDD=5V.
10
25
40
k
VDD=3V.
TBD
tw(RSTL)out Generated reset pulse duration
External pin or
internal reset sources
30
s
th(RSTL)in External reset pulse hold time
6)
20
s
tg(RSTL)in Filtered glitch duration
7)
100
ns
RESET
VDD
WATCH DOG
ST72XXX
LVD
INTERNAL
RON
0.1
F
VDD
0.1
F
VDD
4.7k
EXTERNAL
RESE T
CIRCUIT
8)
RESET CONTROL
O
PT
IO
N
AL
USER
ILLEGAL OPCODE
1
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