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參數(shù)資料
| 型號： | ST7FLITE09Y0M1 |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16 |
| 封裝： | 0.150 INCH, PLASTIC, SOP-16 |
| 文件頁數(shù)： | 51/111頁 |
| 文件大?。?/td> | 671K |
| 代理商： | ST7FLITE09Y0M1 |
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ST7FLITE0
44/111
LITE TIMER (Cont’d)
– When using an external interrupt to wake up the
microcontroller, reinitialize the corresponding I/O
as “Input Pull-up with Interrupt” before executing
the HALT instruction. The main reason for this is
that the I/O may be wrongly configured due to ex-
ternal interference or by an unforeseen logical
condition.
– For the same reason, reinitialize the level sensi-
tiveness of each external interrupt as a precau-
tionary measure.
– The opcode for the HALT instruction is 0x8E. To
avoid an unexpected HALT instruction due to a
program counter failure, it is advised to clear all
occurrences of the data value 0x8E from memo-
ry. For example, avoid defining a constant in
ROM with the value 0x8E.
– As the HALT instruction clears the I bit in the CC
register to allow interrupts, the user may choose
to clear all pending interrupt bits before execut-
ing the HALT instruction. This avoids entering
other peripheral interrupt routines after executing
the external interrupt routine corresponding to
the wake-up event (reset or external interrupt).
Input Capture
The 8-bit input capture register is used to latch the
free-running upcounter after a rising or falling edge
is detected on the ICAP1 pin. When an input cap-
ture occurs, the ICF bit is set and the LTICR regis-
ter contains the MSB of the free-running up-
counter. An interrupt is generated if the ICIE bit is
set. The ICF bit is cleared by reading the LTICR
register.
The LTICR is a read only register and always con-
tains the data from the last input capture. Input
capture is inhibited if the ICF bit is set.
11.1.4 Low Power Modes
11.1.5 Interrupts
Note: The TBF and ICF interrupt events are con-
nected to separate interrupt vectors (see Inter-
rupts chapter).
They generates an interrupt if the enable bit is set
in the LTCSR register and the interrupt mask in the
CC register is reset (RIM instruction).
Figure 31. Input Capture Timing Diagram.
Mode
Description
SLOW
No effect on Lite timer (this peripheral
is driven directly by fOSC/32)
WAIT
No effect on Lite timer
HALT
No effect on Lite timer
Interrupt
Event
Flag
Enable
Control
Bit
Exit
from
Wait
Exit
from
Halt
Timebase
Event
TBF
TBIE
Yes
IC Event
ICF
ICIE
Yes
No
04h
8-bit COUNTER
t
01h
fOSC/32
xxh
02h
03h
05h
06h
07h
04h
LTIC PIN
ICF FLAG
LTICR REGISTER
CLEARED
4
s
(@ 8MHz fOSC)
fCPU
BY S/W
07h
READING
LTIC REGISTER
1
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| ST7FLITE09Y0M3 | 功能描述:8位微控制器 -MCU Flash 1.5K SPI Intrf RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT |
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| ST7FLITE09Y0M6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| ST7FLITE09Y0U6 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
| ST7FLITE09Y0U6TR | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:8-bit microcontroller with single voltage Flash memory, data EEPROM, ADC, timers, SPI |
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