參數(shù)資料
型號(hào)： ST7FLITE09Y0M1
廠商： STMICROELECTRONICS
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝： 0.150 INCH, PLASTIC, SOP-16
文件頁(yè)數(shù)： 50/111頁(yè)
文件大?。?/td> 671K
代理商： ST7FLITE09Y0M1
ST7FLITE0
43/111
LITE TIMER (Cont’d)
11.1.3 Functional Description
The value of the 8-bit counter cannot be read or
written by software. After an MCU reset, it starts
incrementing from 0 at a frequency of fOSC/32. A
counter overflow event occurs when the counter
rolls over from F9h to 00h. If fOSC = 8 MHz, then
the time period between two counter overflow
events is 1 ms. This period can be doubled by set-
ting the TB bit in the LTCSR register.
When the timer overflows, the TBF bit is set by
hardware and an interrupt request is generated if
the TBIE is set. The TBF bit is cleared by software
reading the LTCSR register.
11.1.3.1 Watchdog
When enabled using the WDGE bit, the Watchdog
generates a reset after 2 ms (@ = 8 MHz fOSC).
To prevent this watchdog reset occuring, software
must set the WDGD bit. The WDGD bit is cleared
by hardware after tWDG. This means that software
must write to the WDGD bit at regular intervals to
prevent a watchdog reset occurring. Refer to Fig-
ure 30.
Note: Software can use the timebase feature to
set the WDGD bit at 1 or 2 ms intervals.
A Watchdog reset can be forced at any time by
setting the WDGRF bit.
The WDGRF bit also acts as a flag, indicating that
the Watchdog was the source of the reset. It is au-
tomatically cleared after it has been read.
Caution: When the WDGRF bit is set, software
must clear it, otherwise the next time the watchdog
is enabled (by hardware or software), the micro-
controller will be immediately reset.
Hardware Watchdog Option
If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGE bit in
the LTCSR is not used.
Refer to the Option Byte description in the ”device
configuration and ordering information” section.
Using Halt Mode with the Watchdog (option)
If the Watchdog reset on HALT option is not se-
lected by option byte, the Halt mode can be used
when the watchdog is enabled.
In this case, the HALT instruction stops the oscilla-
tor. When the oscillator is stopped, the Lite Timer
stops counting and is no longer able to generate a
Watchdog reset until the microcontroller receives
an external interrupt or a reset.
If an external interrupt is received, the WDG re-
starts counting after 256 CPU clocks. If a reset is
generated, the Watchdog is disabled (reset state).
Recommendations
– Make sure that an external event is available to
wake up the microcontroller from Halt mode.
– Before executing the HALT instruction, refresh
the WDGD bit, to avoid an unexpected Watch-
dog reset immediately after waking up the micro-
controller.
Figure 30. Watchdog Timing Diagram
tWDG
fWDG
INTERNAL
WATCHDOG
RESET
WDGD BIT
SOFTW ARE SETS
WDGD BIT
HARDWARE CLEARS
WDGD BIT
WATCHDOG RESET
(2ms @ 8MHz fOSC)
1
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