參數(shù)資料
型號(hào): ST7FLITE09Y0M1
廠商: STMICROELECTRONICS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PDSO16
封裝: 0.150 INCH, PLASTIC, SOP-16
文件頁(yè)數(shù): 75/111頁(yè)
文件大小: 671K
代理商: ST7FLITE09Y0M1
ST7FLITE0
66/111
8-BIT A/D CONVERTER (ADC) (Cont’d)
11.4.6 Register Description
CONTROL/STATUS REGISTER (ADCCSR)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7 = EOC
Conversion Complete
This bit is set by hardware. It is cleared by soft-
ware reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register
Bit 6 = SPEED
ADC clock selection
This bit is set and cleared by software. It is used
together with the SLOW bit to configure the ADC
clock speed. Refer to the table in the SLOW bit de-
scription.
Bit 5 = ADON
A/D Converter On
This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on
Bit 4:3 = Reserved.
must always be cleared.
Bits 2:0 = CH[2:0]
Channel Selection
These bits are set and cleared by software. They
select the analog input to convert.
*Note: The number of pins AND the channel selec-
tion varies according to the device. Refer to the de-
vice pinout.
DATA REGISTER (ADCDR)
Read Only
Reset Value: 0000 0000 (00h)
Bits 7:0 = D[7:0]
Analog Converted Value
This register contains the converted analog value
in the range 00h to FFh.
Note: Reading this register reset the EOC flag.
AMPLIFIER CONTROL REGISTER (ADCAMP)
Read/Write
Reset Value: 0000 0000 (00h)
Bit 7:4 = Reserved. Forced by hardware to 0.
Bit 3 = SLOW
Slow mode
This bit is set and cleared by software. It is used
together with the SPEED bit to configure the ADC
clock speed as shown on the table below.
Bit 2 = AMPON
Amplifier Control Bit
This bit is set and cleared by software.
0: Amplifier off
1: Amplifier on
Note: When AMPON=1 it is mandatory that fADC
be less than or equal to 2 MHz.
Bit 1:0 = Reserved. Forced by hardware to 0.
70
EOC
SPEED ADON
0
CH2
CH1
CH0
Channel Pin*
CH2
CH1
CH0
AIN0
0
AIN1
0
1
AIN2
0
1
0
AIN3
0
1
AIN4
1
0
70
D7
D6
D5
D4
D3
D2
D1
D0
70
0
SLOW AMPON
0
fADC
SLOW SPEED
fCPU/2
00
fCPU
01
fCPU/4
1x
1
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