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參數(shù)資料
| 型號： | ST52F514 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI |
| 中文描述： | 8位重癥監(jiān)護病房智能控制單元兩個定時器/的PWM，模數(shù)轉(zhuǎn)換器，I2C，SPI和脊髓損傷 |
| 文件頁數(shù)： | 97/106頁 |
| 文件大?。?/td> | 1340K |
| 代理商： | ST52F514 |
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ST52F510/F513/F514
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Figure 15.2 Serial Peripheral Interface Block Diagram
Procedure
– Select the SPR0, SPR1 and SPR2 bits to define
the serial clock baud rate (see SPI_CR register).
– Select the CPOL and CPHA bits to define one of
the four relationships between the data transfer
and the serial clock (see Figure 15.4).
– The SS pin must be connected to a high level
signal during the complete byte transmit se-
quence.
– The MSTR and SPE bits must be set (they re-
main set only if the SS pin is connected to a high
level signal).
In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.
Transmit sequence
Transmit sequence begins when a byte is written in
the SPI_OUT register.
The data byte is loaded in parallel into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.
When data transfer is complete:
– The SPIF bit is set by hardware
– An interrupt is generated if the SPIE bit is set.
During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the SPI_IN register is
read, the SPI peripheral returns this buffered
value. Clearing the SPIF bit is performed by the
following software sequence:
1. An access to the SPI_STATUS_CR register
while the SPIF bit is set
2. A read to the SPI_IN register.
Note:
While the SPIF bit is set, all writes to the
SPI_OUT
register
are
SPI_STATUS_CR register is read.
inhibited
until
the
SPI_IN
Read Buffer
8-Bit Shift Register
Write
Read
Internal Bus
SPI
STATE
SPIE
SPE
MSTR
CPHA
SPR0
SPR1
CPOL
SPIF WCOL
MODF
SERIAL
CLOCK
GENERATOR
MOSI
MISO
SS
SCK
CONTROL
SPI_CR
SPI_STATUS_CR
-
IT
request
MASTER
CONTROL
SPR2
OR
SSI
SSM
SOD
SPI_OUT
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