參數(shù)資料
型號: ST52F514
廠商: 意法半導(dǎo)體
英文描述: 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
中文描述: 8位重癥監(jiān)護病房智能控制單元兩個定時器/的PWM,模數(shù)轉(zhuǎn)換器,I2C,SPI和脊髓損傷
文件頁數(shù): 25/106頁
文件大?。?/td> 1340K
代理商: ST52F514
ST52F510/F513/F514
25/106
3.7 Configuration Registers & Option Bytes
The
ST52F510/F513/F514
Registers bench consists of a file of 8-bit registers
that allows the configuration of all the ICU blocks.
The registers are located inside the block they
configure in order to obtain greater flexibility and
modularity in the design of new family devices. In
the Configuration Registers, each bit has a
peculiar use, so the logic level of each of them
must be considered.
Some special configuration data, that needs to be
load at the start-up and not further changed, are
stored in Option Bytes. These are loaded only
during the device programming phase. See Table
3.3 and Section 4 for a detailed description of the
Option Bytes.
The Configuration Registers are readable and
writable; the addresses refer to the same register
both in read and in write. In order to access the
Configuration Register the user can work in
several
modes
by
utilizing
instructions:
Configuration
the
following
I
LDCI: loads the immediate value in the
Configuration Register specified and is the most
commonly used to write configuration data.
I
LDCR: loads the Configuration Register
specified with the contents of the specified
Register File location, allowing a parametric
configuration.
I
LDCE:
loads the
specified with the contents of the specified
Program/Data Memory location, allowing the
configuration data to be taken from a table.
I
LDCNF: loads the Register File location
specified with the contents of the Configuration
Register indicated, allowing for the inspection of
the configuration of the device (permitting safe
run-time modifications).
In order to simplify the concept, a mnemonic name
is assigned to each register. The same name is
used in Visual FIVE development tools. The list of
the Configuration Registers is shown in Table 3.4.
Configuration
Register
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