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參數資料
| 型號： | ST52F514 |
| 廠商： | 意法半導體 |
| 英文描述： | 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI |
| 中文描述： | 8位重癥監(jiān)護病房智能控制單元兩個定時器/的PWM，模數轉換器，I2C，SPI和脊髓損傷 |
| 文件頁數： | 87/106頁 |
| 文件大?。?/td> | 1340K |
| 代理商： | ST52F514 |
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ST52F510/F513/F514
87/106
Acknowledge may be enabled and disabled via
software.
The I
2
C interface address and/or general call
address can be selected via software.
The speed of the I
2
C interface may be selected
between Standard (0-100KHz) and Fast I
2
C (100-
400KHz).
14.3.3 SDA/SCL Line Control.
Transmitter mode: the interface holds the clock line
low before transmission, in order to wait for the
microcontroller to write the byte in the Data
Register.
Receiver mode: the interface holds the clock line
low after reception to wait for the microcontroller to
read the byte in the Data Register.
SCL frequency is controlled by a programmable
clock divider which depends on the I
2
C bus mode.
When the I
2
C cell is enabled, the SDA and SCL
pins must be configured as floating open-drain I/O.
The value of the external pull-up resistance used
depends on the application.
14.4 Functional Description
By default the I
2
C interface operates in Slave
mode (M/SL bit is cleared) except when it initiates
a transmit or receive sequence.
First, the interface frequency must be configured
using the related bits of the Configuration
Registers.
14.4.1 Slave Mode.
As soon as a start condition is detected, the
address is received from the SDA line and sent to
the shift register; then it is compared with the
address of the interface or the General Call
address (if selected by software).
Figure 14.2 I
2
C Interface Block Diagram
DATA REGISTER
DATA SHIFT REGISTER
COMPARATOR
OWN ADDRESS REGISTER (OAR)
CLOCK CONTROL REGISTER (I2C_CCR)
STATUS REGISTER 1 (I2C_SR1)
CONTROL REGISTER (I2C_CR)
SDA
SCL
CONTROL LOGIC
STATUS REGISTER 2 (I2C_SR2)
INTERRUPT
CLOCK CONTROL
DATA CONTROL
SCL
SDA
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