參數(shù)資料
型號： ST52F514
廠商： 意法半導(dǎo)體
英文描述： 8-BIT INTELLIGENT CONTROLLER UNIT ICU Two Timer/PWMs, ADC, I2C, SPI, SCI
中文描述： 8位重癥監(jiān)護(hù)病房智能控制單元兩個定時器/的PWM，模數(shù)轉(zhuǎn)換器，I2C，SPI和脊髓損傷
文件頁數(shù)： 60/106頁
文件大?。?/td> 1340K
代理商： ST52F514
ST52F510/F513/F514
60/106
9 INSTRUCTION SET
ST52F510/F513/F514 supplies 107 (98 + 9 Fuzzy)
instructions that perform computations and control
the device. Computational time required for each
instruction consists of one clock pulse for each
Cycle plus 2 clock pulses for the decoding phase.
Total computation time for each instruction is
reported in Table 9.1
The ALU of ST52F510/F513/F514 can perform
multiplication
(MULT)
Multiplication is performed by using 8 bit operands
storing the result in 2 registers (16 bit values), see
Figure 2.3.
Division is performed between a 16 bit dividend
and an 8 bit divider, the result and the remainder
are stored in two 8-bit registers (see Figure 2.4).
9.1 Addressing Modes
ST52F510/F513/F514
instructions
following addressing modes:
I
Inherent: this instruction type does not require
an operand because the opcode specifies all the
information necessary to carry out the
instruction. Examples: NOP, SCF.
I
Immediate: these instructions have an operand
as a source immediate value. Examples: LDRC,
ADDI.
I
Direct: the operands of these instructions are
specified with the direct addresses. The
and
division
(DIV).
allow
the
operands can refer (according to the opcode) to
addresses belonging to the different addressing
spaces. Example: SUB, LDRE.
I
Indirect: data addresses that are required are
found in the locations specified as operands.
Both source and/or destination operands can be
addressed indirectly. The operands can refer,
(according to the opcode) to addresses
belonging to different addressing spaces.
Examples: LDRR(reg1),(reg2);
LDER mem_addr,(reg1).
I
Bit Direct: operands of these instructions directly
address the bits of the specified Register File
locations. Examples: BSET, BTEST.
9.2 Instruction Types
ST52F510/F513/F514 supplies the following
instruction types:
I
Load Instructions
I
Arithmetic and Logic Instructions
I
Bitwise instructions
I
Jump Instructions
I
Interrupt Management Instructions
I
Control Instructions
The instructions are listed in Table 9.1
Table 9.1 Instruction Set
Load Instructions
Mnemonic
Instruction
Bytes
Cycles
Z
S
C
BLKSET
BLKSET const
2
(*)
-
-
-
GETPG
GETPG regx
2
7
-
-
-
LDCE
LDCE confx,memy
3
8/9
-
-
-
LDCI
LDCI confx, const
3
7
-
-
-
LDCNF
LDCNF regx, conf
3
7
-
-
-
LDCR
LDCR confx, regy
3
8
-
-
-
LDER
LDER memx, regy
3
10
-
-
-
LDER
LDER (regx),(regy)
3
11
-
-
-
LDER
LDER (regx), regy
3
10
-
-
-
LDER
LDER memx,(regy)
3
11
-
-
-
LDFR
LDFR fuzzyx, regy
3
8
-
-
-
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